spear-09-p022 STMicroelectronics, spear-09-p022 Datasheet
spear-09-p022
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spear-09-p022 Summary of contents
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... System on chip. The device integrates two ARM 926 cores with a large set of proven IPs and a big configurable logic block that allow very fast customization of unique and/or proprietary solution. Package - PBGA420(23x23x1.81mm) Rev 1 SPEAR-09-P022 Preliminary Data PBGA420 Packing Tray 1/37 www.st.com 1 ...
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... ML1 Multi layer CPU subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.6 ICM3 - Basic subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 Main Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 7.1 CPU subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.1 4.1.2 4.2 Clock and Reset System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3.1 4.3.2 4.4 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.4.1 4.4.2 2/37 USB 2.0 Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SSTL_2/SSTL_18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CPU ARM 926EJ Crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 RTC crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 RTC crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SPEAR-09-P022 ...
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... SPEAR-09-P022 4.5 Ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.6 USB2 Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.7 USB2 Device Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.8 Low jitter PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.9 Reconfigurable logic array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.9.1 4.9.2 4.9.3 4.9.4 4.10 Other interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.10.1 4.10.2 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Custom project development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Customization process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ADC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 UART ...
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... Table 6. ICM2 - Application subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 7. ICM4 - High speed connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 8. ML1 Multi layer CPU subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 9. ICM3 - Basic subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 10. Main oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 11. RTC oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 12. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 13. DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 14. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4/37 SPEAR-09-P022 ...
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... SPEAR-09-P022 List of figures Figure 1. Main SPEAr Plus600 functional interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3. Crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 4. Crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 5. RTC crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 6. RTC crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 7. PBGA420 Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 List of figures 5/37 ...
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... Reference documentation Reference documentation 1. ARM926EJ-S - Technical Reference Manual 2. AMBA 2.0 Specification 3. EIA/JESD8-9 Specification 4. USB2.0 Specification 5. OHCI Specification 6. EHCI Specification 7. USB Specification 8. IEEE 802.3 Specification Bus Specification 6/37 SPEAR-09-P022 ...
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... SPEAR-09-P022 1 Product Overview An outline picture of the main SPEAr Plus600 functional interfaces is shown in Figure 1. Main SPEAr Plus600 functional interfaces 1.1 Features The following main functionalities are implemented in the SPEAr Plus600 SoC device: ● Dual ARM926EJ-S core @333Hhz, 16KB-I/D cache, configurable TMC-I/D size, MMU, TLB, JTAG and ETM trace module (multiplexed interfaces). ● ...
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... Internal memory pool (128Kbyte) full configurable. – external/internal source clock (some of these programmable). – Three memory path toward the SDRAM controller to ensure a good bandwidth. ● Architecture easily extensible. ● External memory bandwidth of each master tuneable to meet the target performances of different applications. 8/37 SPEAR-09-P022 ...
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... SPEAR-09-P022 1.3 Block diagram Figure 2. Block diagram SPEArPlus600 Configurable Cell Array Subsystem SRAM SRAM 32KB 32KB Cell Array (Applic. configurable) SRAM SRAM 32KB 32KB ARM Subsystem CPU2 CPU1 ARM926EJS APB ARM926EJS Tmr 16kI/16kD 16kI/16kD Coproces. Cache Int GPIO Cache Tcm -I/D I ctr ...
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... Input Test Clock D16 Input Test Data Input D15 Input Test Mode Select P4 I/O Programmable Logic I/O SPEAR-09-P022 6, here follows the pin list, sorted by Pin Type Analog buffer 2.5V tolerant TTL input buffer, 3.3 V tolerant, PD TTL Schmitt trigger input buffer, 3.3 V tolerant, PU TTL output buffer, 3 ...
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... SPEAR-09-P022 Table 2. Pin description by functional group (continued) Group Signal name PL_GPIO_1 PL_GPIO_2 PL_GPIO_3 PL_GPIO_4 PL_GPIO_5 PL_GPIO_6 PL_GPIO_7 PL_GPIO_8 PL_GPIO_9 PL_GPIO_10 PL_GPIO_11 PL_GPIO_12 PL_GPIO_13 PL_GPIO_14 PL_GPIO_15 PL_GPIO_16 PL_GPIO_17 PL PL_GPIO_18 PL_GPIO_19 PL_GPIO_20 PL_GPIO_21 PL_GPIO_22 PL_GPIO_23 PL_GPIO_24 PL_GPIO_25 PL_GPIO_26 PL_GPIO_27 PL_GPIO_28 PL_GPIO_29 PL_GPIO_30 ...
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... PL_GPIO_62 PL_GPIO_63 PL_GPIO_64 PL_GPIO_65 PL_GPIO_66 PL_GPIO_67 PL_GPIO_68 PL_GPIO_69 PL_GPIO_70 12/37 Ball Direction Function I/O Programmable Logic I SPEAR-09-P022 Pin Type TTL BIDIR buffer, 3.3V capable, 4mA 3.3V tolerant, PU ...
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... SPEAR-09-P022 Table 2. Pin description by functional group (continued) Group Signal name PL_GPIO_71 PL_GPIO_72 PL_GPIO_73 PL_GPIO_74 PL_GPIO_75 PL_GPIO_76 PL_GPIO_77 PL_GPIO_78 PL PL_GPIO_79 PL_GPIO_80 PL_GPIO_81 PL_GPIO_82 PL_GPIO_83 PL_CLK_1 PL_CLK_2 PL_CLK_3 PL_CLK_4 GMII_TXCLK GMII_TXCLK125 MII_TXCLK TXD_0 TXD_1 TXD_2 TXD_3 GMII_TXD_4 Ethernet GMII_TXD_5 GMII_TXD_6 GMII_TXD_7 TX_ER ...
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... Y20 Y21 Y22 W22 W21 W20 Output LCD Data V20 V21 V22 U22 U21 SPEAR-09-P022 Pin Type TTL Input buffer 3.3V tolerant, PD TTL BIDIR buffer 3.3V capable, 8mA 3.3V tolerant, PD TTL Input buffer 3.3V tolerant, PD TTL BIDIR buffer 3.3V capable, 4mA 3.3V tolerant, PD TTL Output buffer 3 ...
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... SPEAR-09-P022 Table 2. Pin description by functional group (continued) Group Signal name CLD_11 CLD_12 CLD_13 CLD_14 CLD_15 CLD_16 CLD_17 CLD_18 CLD_19 CLD_20 CLD_21 LCD I/F CLD_22 CLD_23 CLAC CLCP CLFP CLLP CLLE CLPOWER DDR_ADD_0 DDR_ADD_1 DDR_ADD_2 DDR_ADD_3 DDR_ADD_4 DDR_ADD_5 DDR_ADD_6 DDR I/F DDR_ADD_7 DDR_ADD_8 ...
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... Y12 AB12 AA12 AB13 Differential lower Data Strobe AA13 AA11 Output Lower Data Mask Y13 Lower Gate Open AB15 AA16 AB16 I/O Data Lines Y16 (Upper byte) Y15 Y14 AB14 SPEAR-09-P022 Pin Type SSTL_2/SSTL_18 Differential SSTL_2/SSTL_18 SSTL_2/SSTL_18 SSTL_2/SSTL_18 Differential SSTL_2/SSTL_18 SSTL_2/SSTL_18 ...
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... SPEAR-09-P022 Table 2. Pin description by functional group (continued) Group Signal name DDR_DATA_15 DDR_DQS_1 DDR_nDQS_1 DDR_DM_1 DDR_GATE_1 DDR I/F DDR_VREF DDR_COMP_2V5 DDR_COMP_GND DDR_COMP_1V8 DDR2_EN DEV_DP DEV_DM DEV_VBUS HOST1_DP HOST1_DM HOST1_VBUS USB HOST1_OVRC HOST2_DP HOST2_DM HOST2_VBUS HOST2_OVRC USB_RREF MCLK_XI Master Clock MCLK_XO RTC_XI RTC ...
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... AB18 Input Serial Data In Y18 I/O Serial data In/Out Y19 I/O Serial Clock H19 I/O Data SPEAR-09-P022 Pin Type TTL Output Buffer 3.3V capable, 4mA TTL BIDIR buffer 3.3V capable, 8mA 3.3V tolerant, PU TTL Output Buffer 3.3V capable, 4mA TTL Input Buffer 3.3V tolerant, PD TTL Output Buffer 3.3V capable, 4mA TTL Input Buffer 3 ...
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... SPEAR-09-P022 Table 2. Pin description by functional group (continued) Group Signal name NF_IO_1 NF_IO_2 NF_IO_3 NF_IO_4 NF_IO_5 NF_IO_6 NF_IO_7 NAND FLASH NF_CE I/F NF_RE NF_WE NF_ALE NF_CLE NF_WP NF_RB MRESET PH0 PH0n PH1 PH1n PH2 PH2n PH3 PH3n LVDS PH4 I/F PH4n PH5 PH5n ...
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... W17 DD DDR_PLL_V T17 DD LVDS_V F11, F12, F14 DD RTC_V B10 DD 20/37 Ball Direction Function General purpose I/O B11 Input with LVDS transceiver E11 Output Configuration Ball SPEAR-09-P022 Pin Type LVDS Receiver Analog 3.3V capable Value 3.3 V 1.0 V 2.5 V 1.0 V 3.3 V 2.5 V 1.0 V 3.3 V 2.5 V 1.0 V 3.3 V 1.0 V 2.5 V 1 ...
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... SPEAR-09-P022 2.2 Special IOs 2.2.1 USB 2.0 Transceiver SPEAr Plus600 has three USB 2.0 Multimode ATX transceivers. One transceiver will be used by the USB Device controller, and two will be used by the Hosts. These are all integrated into a single USB three-PHY macro. 2.2.2 SSTL_2/SSTL_18 T.B.D. 2.2.3 LVDS T.B.D. Pin description ...
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... JPEG codec 0xD17F.FFFF IrDA 0xD1FF.FFFF FSMC 0xD27F.FFFF FSMC 0xD7FF.FFFF SRAM SPEAR-09-P022 NOTES DDR1 or DDR2 Programmable Logic Array Low Speed connection Application Subsystem High Speed Connection Multi Layer CPU subsystem Basic Subsystem NOTES Reserved NAND Flash Controller NAND Flash Memory ...
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... SPEAR-09-P022 3.3 ICM2 - Application subsystem Table 6. ICM2 - Application subsystem START ADDRESS 0xD800.0000 0xD808.0000 0xD810.0000 0xD818.0000 0xD820.0000 0xD828.0000 3.4 ICM4 - High speed connection Table 7. ICM4 - High speed connection START ADDRESS 0xE000.0000 0xE080.0000 0xE100.0000 0xE110.0000 0xE120.0000 0xE130.0000 0xE180.0000 0xE190.0000 0xE1A0.0000 0xE200.0000 0xE210.0000 0xE220.0000 0xE280.0000 0xE290 ...
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... SDRAM Controller 0xFC87.FFFF Timer 0xFC8F.FFFF Watch Dog Timer 0xFC97.FFFF Real Time Clock 0xFC9F.FFFF General Purpose I/O 0xFCA7.FFFF System Controller 0xFCAF.FFFF Miscellaneous Registers 0xFEFF.FFFF - 0xFFFF.FFFF Internal Rom SPEAR-09-P022 NOTES Reserved Reserved NOTES Reserved Boot BUS APB APB AHB AHB AHB AHB ...
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... SPEAR-09-P022 4 Main Blocks 4.1 7.1 CPU subsystem 4.1.1 Overview Each CPU sub-system includes the following blocks: ● ARM 926EJS ● Two timer channels ● One GPIO block (8 I/O lines) ● Two Interrupt Controller (32 IRQ lines) 4.1.2 CPU ARM 926EJ-S The processor is the powerful ARM926EJ-S, targeted for multi-tasking applications. ...
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... PCBs, metal shielding etc., allowing sensible cost saving for customers. Note: 1 This frequency is based on the PLL1. 2 This frequency is based on the PLL2. 4.3 Main oscillator 4.3.1 Crystal connection Figure 3. Crystal connection 26/ MHz SPEAR-09-P022 ...
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... SPEAR-09-P022 4.3.2 Crystal equivalent model Figure 4. Crystal equivalent model the parasitic capacitance of the crystal package 2. Cl1 and Cl2 are the capacitance on each resonator PAD Table 10. Main oscillator characteristics Supplier Epson (E31821) Raltron (M3000) KSS (KSS3KF) 4.4 RTC oscillator 4.4.1 RTC crystal connection Figure 5 ...
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... Main Blocks 4.4.2 RTC crystal equivalent model Figure 6. RTC crystal equivalent model the parasitic capacitance of the crystal package 2. Cl1 and Cl2 are the capacitance on each resonator PAD Table 11. RTC oscillator characteristics Supplier Ecliptek 28/ Rm(KOhms) Lm(mH) <65 10 SPEAR-09-P022 Xo 2 GND Cm(fF) Co(pF) 1.9 0.85 ...
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... SPEAR-09-P022 4.5 Ethernet controller ● Compliant with the IEEE 802.3-2002 standard. ● GMII or MII Interface to the external PHY. ● It supports 10/100/1000 Mbps data transfer rates with any one or a combination of the PHY interfaces above; ● Local FIFO available (4Kbyte RX, 2Kbyte TX). ...
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... An AHB master for data transfer to system memory is provided, supporting 8, 16, and 32-bit wide data transactions on the AHB bus. ● A USB Plug Detect (UPD) which detects the connection of a cable. 4.8 Low jitter PLL Within the USB Hosts and device a local Low Jitter PLL is provided to meet the USB2.0 specification requirements. 30/37 SPEAR-09-P022 ...
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... SPEAR-09-P022 4.9 Reconfigurable logic array 4.9.1 Overview The Configurable Logic array consists of an embedded macro where it is possible to implement a custom project by mapping up to 600K equivalent gates. This macro is interfaced with the rest of the system by some AHB bus, some memory channels and has a direct connection to the 1st ARM processor internal bus. In this way is also possible to customize the TCM memory or add a coprocessor using this macro ...
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... Programmable choice of interface operation SPI, Microwire or TI synchronous serial ● Programmable data frame size from bit. ● The SPI controllers can deal with Master and slave mode. ● A connection with general purpose DMA is provided to reduce the CPU load. 32/37 SPEAR-09-P022 ...
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... SPEAR-09-P022 5 Electrical characteristics 5.1 Absolute maximum ratings This product contains devices to protect the inputs against damage due to high static voltages; however it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. Table 12. Absolute maximum ratings ...
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... Supply voltage PLL DD V OSC Supply voltage oscillator DD V DDR1 Supply voltage DRAM I/F (DDR1 DDR2 Supply voltage DRAM I/F (DDR2 RTC Supply voltage RTC DD T Operating temperature OP 34/37 Parameter Min. 0.95 3 2.25 2.25 2.25 1.7 0.95 -40 SPEAR-09-P022 Typ. Max. Unit 1 1.05 V 3.3 3.6 V 2.5 2.75 V 2.5 2.75 V 2.5 2.75 V 1 °C ...
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... SPEAR-09-P022 6 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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... Revision history 7 Revision history Table 14. Document revision history Date 24-Jan-2007 28-Feb-2007 36/37 Revision 1 Initial release. 2 Corrected typos. SPEAR-09-P022 Changes ...
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... SPEAR-09-P022 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...