xr17l152im Exar Corporation, xr17l152im Datasheet - Page 21
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xr17l152im
Manufacturer Part Number
xr17l152im
Description
3.3v Pci Bus Dual Uart
Manufacturer
Exar Corporation
Datasheet
1.XR17L152IM.pdf
(55 pages)
- Current page: 21 of 55
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XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide
the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further
divides this clock by a programmable divisor between 1 and (2
serial data rate. The sampling clock is used by the transmitter for data bit shifting and receiver for data
sampling. The BRG divisor (DLL and DLM registers) defaults to a random value upon power up. Therefore, the
BRG must be programmed during initialization to the operating data rate.
Programming the Baud Rate Generator Registers DLM and DLL provides the capability for selecting the
operating data rate.
clock at 16X clock rate. At 8X sampling rate, these data rates would double. When using a non-standard data
rate crystal or external clock, the divisor value can be calculated with the following equation(s).
4.1
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16),
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 8),
Programmable Baud Rate Generator
F
IGURE
XTAL1
XTAL2
Table 9
8. B
AUD
shows the standard data rates available with a 14.7456 MHz crystal or external
R
Crystal
Buffer
Osc/
ATE
G
To Channel 1
ENERATOR
Divide by 4
Divide by 1
Prescaler
Prescaler
21
MCR Bit-7=0
MCR Bit-7=1
(default)
16
-1) to obtain a 16X or 8X sampling clock of the
Baud Rate
DLL and DLM
Generator
Registers
Logic
WITH
WITH
8XMODE [1:0]
8XMODE [1:0]
Rate Clock to
and Receiver
Transmitter
16X or 8X
Sampling
DISCONTINUED
IS
IS
áç
áç
áç
áç
1
0
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