xr17l152im Exar Corporation, xr17l152im Datasheet - Page 19

• Manufacturer Part Number: xr17l152im
• Description: 3.3v Pci Bus Dual Uart
• Manufacturer: Exar Corporation

XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
The transmit and receive data registers are defined for channels 0 and 1 with each channel having its own
address as shown in
and transmit data registers in more detail.
Each Channel Normal Receive Data FIFO Address for channels 0 and 1 are at 0x0100 and 0x0300.
Each Channel Normal Transmit Data FIFO Address for Channel 0 and 1 are at 0x0100 and 0x0300.
3.1
Data Bit-31
WITH N
Data Bit-31
PCI Bus
Read n+0 to n+3
Read n+4 to n+7
Write n+0 to n+3
Write n+4 to n+7
W
R
PCI Bus
B7 B6 B5 B4 B3 B2 B1 B0
EAD
RITE
B7 B6 B5 B4 B3 B2 B1 B0
FIFO DATA LOADING AND UNLOADING THROUGH THE DEVICE CONFIGURATION REGISTERS
IN 32-BIT FORMAT
Transmit Data Byte n+3
Etc.
Etc.
RX FIFO,
Receive Data Byte n+3
O
TX FIFO
E
RRORS
Channel 0 to 1 Transmit Data in 32-bit alignment through the Configuration Register Address
Table 2
Channel 0 to 1 ReceiveData in 32-bit alignment through the Configuration Register Address
FIFO Data n+3
FIFO Data n+7
FIFO Data n+3
FIFO Data n+7
for faster loading and unloading. The following paragraphs illustrate the receive
B
B
B7 B6 B5 B4 B3 B2 B1 B0
YTE
YTE
B7 B6 B5 B4 B3 B2 B1 B0
Transmit Data Byte n+2
3
3
Receive Data Byte n+2
FIFO Data n+2
FIFO Data n+6
0x0100 and 0x0300
FIFO Data n+2
FIFO Data n+6
0x0100 and 0x0300
B
B
YTE
YTE
19
B7 B6 B5 B4 B3 B2 B1 B0
2
B7 B6 B5 B4 B3 B2 B1 B0
2
Transmit Data Byte n+1
Receive Data Byte n+1
FIFO Data n+1
FIFO Data n+5
FIFO Data n+1
FIFO Data n+5
B
B
YTE
YTE
1
1
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
DISCONTINUED
Transmit Data Byte n+0
Receive Data Byte n+0
áç
áç
áç
áç
FIFO Data n+0
FIFO Data n+4
FIFO Data n+0
FIFO Data n+4
B
B
YTE
YTE
Data Bit-0
Data Bit-0
0
0
PCI Bus
PCI Bus