xr17l152im Exar Corporation, xr17l152im Datasheet - Page 11

• Manufacturer Part Number: xr17l152im
• Description: 3.3v Pci Bus Dual Uart
• Manufacturer: Exar Corporation

XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
The XR17L152 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and
supports two interrupt schemes. The first scheme is a 2-bit indicator in INT0 register representing the 2
channels with the first 3 bits representing each channel from 0 to 1. This permits the interrupt routine to quickly
vector and serve that UART channel and determine the source(s) in each individual routines. INT0 bit-0
represents the interrupt status for UART channel 0 when its transmitter, receiver, line status, or modem port
status requires service. INT0 bit-1 provides interrupt status for channel 1 and bits 2 to 7 are reserved and
remain at a logic 0.
The second scheme provides detail about the source of the interrupts for each UART channel. All the interrupts
are encoded into a 3-bit code per channel. This 3-bit code represents 7 interrupts corresponding to individual
UART’s transmitter, receiver, line status, modem port status. INT1 and INT2 registers provide the 6-bit interrupt
status for both channels. Bits 8, 9 and 10 represents channel 0 and bits 11,12 and 13 represents channel 1.
Bits 14 to 31 are reserved and remain at logic zero. Both channels interrupt status are available with a single
DWORD read operation. This feature allows the host to quickly vector and serve the interrupts, reducing
service interval, hence, reducing host bandwidth requirements.
GLOBAL INTERRUPT REGISTER (DWORD)
Upon power-up or reset, all bits are a logic 0. A special interrupt condition is generated by the L152 upon
awakening from sleep after both channels were put to sleep mode earlier.
register and its make up.
INT0 [7:0] Channel Interrupt Indicator.
Each bit gives an indication of the channel that has requested for service. Bit-0 represents channel 0 and bit-1
indicates channel 1. Logic one indicates the channel N [1:0] has requested for service. Bits 2 to 7 are reserved
and remain at logic zero The interrupt bit clears after reading the appropriate register of the interrupting
channel register, see Interrupt Clearing section.
1.2.1
0x088-08B
0x08C-08F
0x080
0x084-087
0x090-093
A
DDRESS
A
[A7:A0]
Ox091
Ox092
Ox093
DDRESS
INT3 [31:24]
-
083
The Interrupt Status Register
T
ABLE
T
ANCILLARY1 (read/write)
ANCILLARY2 (read-only)
INTERRUPT (read-only)
ABLE
TIMER (read/write)
MPIO (read/write)
4: D
MPIOSEL
R
MPIOINV
3: D
MPIO3T
R
EGISTER
EGISTER
EVICE
EVICE
INT2 [23:16]
C
C
ONFIGURATION
ONFIGURATION
Read/Write MPIO input polarity select
Read/Write MPIO select
Read/Write MPIO output control
B
TIMERMSB
YTE
MPIOSEL
MPIOINT
SLEEP
[default 0x00-00-00-00]
INT3
R
3 [31:24]
R
EGISTERS SHOWN IN
R
11
EGISTERS SHOWN IN
EAD
/W
RITE
B
INT1 [15:8]
YTE
TIMERLSB
C
MPIOINV
RESET
REGB
OMMENT
INT2
2 [23:16]
DWORD
BYTE
Figure 4
B
ALIGNMENT
YTE
(reserved)
(reserved)
MPIO3T
ALIGNMENT
TIMER
REGA
DVID
INT1
shows the 4-byte interrupt
1 [15:8]
DISCONTINUED
Bits 7-0 = 0xFF
INT0 [7:0]
Bits 7-0 = 0x00
Bits 7-0 = 0x00
áç
áç
áç
áç
R
ESET
B
TIMERCNTL
YTE
8XMODE
MPIOLVL
DREV
S
INT0
TATE
0 [7:0]