xr17l152im Exar Corporation, xr17l152im Datasheet - Page 20

• Manufacturer Part Number: xr17l152im
• Description: 3.3v Pci Bus Dual Uart
• Manufacturer: Exar Corporation

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Each Channel Special Receive FIFO Data Address for channel 0 and 1 are at 0x0180 and 0x380. The Status
and Data bytes must be read in 16 or 32 bits format to maintain data integrity.
The THR and RHR register address for channel 0 to channel 1 is shown in
for each channel 0 tand 1 are located sequentially at address 0x0000 and 0x0200. Transmit data byte is loaded
to the THR when writing to that address and receive data is unloaded from the RHR register when reading that
address. Both THR and RHR registers are 16C550 compatible in 8-bit format, so each bus operation can only
write or read in bytes.
There are 2 UARTs [channels 1:0] in the L152. Each has its own 64-byte of transmit and receive FIFO, a set of
16550 compatible control and status registers, and a baud rate generator for individual channel data rate
setting. Eight additional registers per UART were added for the EXAR enhanced features.
3.2
4.0 UART
Data Bit-31
WITH LSR
Read n+0 to n+1
Read n+2 to n+3
PCI Bus
R
EAD
B7 B6 B5 B4 B3 B2 B1 B0
FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR
AND RHR IN 8-BIT FORMAT
Receive Data Byte n+1
RX FIFO,
Etc
E
T
ABLE
RRORS
CH0 0x000 Read RHR
CH1 0x200 Read RHR
CH0 0x000 Write THR
CH1 0x200 Write THR
8: T
RANSMIT AND
THR and RHR Address Locations For CH0 to CH1 (16C550 Compatible)
Channel 0 to 1 Receive Data with Line Status Register in a 32-bit alignment through
FIFO Data n+1
FIFO Data n+3
B
B7 B6 B5 B4 B3 B2 B1 B0
YTE
Line Status Register n+1
3
the Configuration Register Address 0x0180 and 0x0380
R
ECEIVE
Bit-7
Bit-7
Bit-7
Bit-7
D
ATA
Bit-6
Bit-6
Bit-6
Bit-6
R
LSR n+1
LSR n+3
B
EGISTER IN
YTE
20
Bit-5
Bit-5
Bit-5
Bit-5
B7 B6 B5 B4 B3 B2 B1 B0
2
Receive Data Byte n+0
Bit-4
Bit-4
Bit-4
Bit-4
B
YTE FORMAT
Bit-3
Bit-3
Bit-3
Bit-3
FIFO Data n+0
FIFO Data n+2
B
Bit-2
Bit-2
Bit-2
Bit-2
YTE
Table 8
, 16C550
1
3.3V PCI BUS DUAL UART
Bit-1
Bit-1
Bit-1
Bit-1
B7 B6 B5 B4 B3 B2 B1 B0
below. The THR and RHR
Line Status Register n+0
COMPATIBLE
Bit-0
Bit-0
Bit-0
Bit-0
LSR n+0
LSR n+2
B
YTE
XR17L152
REV. 1.1.0
Data Bit-0
0
PCI Bus