lf3370 LOGIC Devices Incorporated, lf3370 Datasheet - Page 8

• Manufacturer Part Number: lf3370
• Description: High-definition Video Format Converter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
halfband filters to the data flowing
through the LF3370. A latched HIGH to
LOW transition on SYNC control signal is
needed to initialize the device to mark the
beginning of valid data.
In addition, if 4:2:2 interleaved video data
is desired for input or output, a HIGH to
LOW transition on SYNC must be
registered by a simultaneous rising edge of
CLK and CLK/2. CLK/2 is an internal
clock that must be synchronized to CLK
by use of RESET only if the core is running
at half the rate of CLK (see RESET
discussio n and Figures 4 & 5).
Furthermore, SYNC is used to identify one
interleaved data set from another. For
example, in the case of interleaved
Chroma, Cb and Cr samples must be
properly demultiplexed and synchro-
nized for processing.
To differentiate a Cb sample from Cr, there
needs to be a HIGH to LOW transition on
SYNC on the first Cb sample (see Figure 4
& 5); SYNC can also be toggled on every
Cb sample for re-synchronization.
word, SYNC may be used only once in
device initialization and kept low until re-
In the case that Cb is the first valid data
F
IGURE
COUNTER
HBLANK
C'
D'
B'
20-bit
A'
12-0*
12-0*
12-0*
CLK
12-0*
HF
HF
10.
0
1
*
Data values at output of Input LUT section
In this example, HF
D
D
D
D
HBLANK
N
N
N
N
HBLANK Word A
HBLANK Word B
HBLANK Word C
HBLANK Word D
1
2
0
0
Count Value is set to 3 and HF
AND
D
D
D
D
3
C
N+3
N+3
N+3
N+3
1
OUNTER
D
D
D
D
4
N+4
N+4
N+4
N+4
2
synchronization is desired. Therefore,
when there is a HIGH to LOW transition
on SYNC, the following is assumed: Cb
will occur on the first LOW on SYNC that
is latched, Cb will occur every two clock
cycles if interleaved Chroma is presented
to the input port B
4 clock cycles if single channel 4:2:2
interleaved video is presented to the input
port A
SYNC control signal is also used to
synchronize the interpolation/decimation
output data from the Half-Band Filter to
the Output Multiplexer. This synchroniza-
tion is done automatically.
RESET
RESET should be used when initializing
the device for proper operation. It is used
to synchronize the LF3370 core clock to
the master clock. In the case that single
channel 4:2:2 interleaved video data is
desired either on the input or output, thus
using only one input or one output port
(not including Key data), the internal
clock rate will be half (CLK/2) of the
master clock rate (CLK). In this case,
RESET is needed to synchronize the rising
edge of CLK/2 to a known rising edge of
CLK (see Figure 4). For example, after
configuring the LF3370 and before
D
D
D
D
5
N+5
N+5
N+5
N+5
3
12-0
D
D
D
D
6
1
N+6
N+6
N+6
N+6
.
4
Count Value is set to 5
D
D
D
D
7
5
N+7
N+7
N+7
N+7
12-0
D
D
D
D
8
8
, Cb will occur every
N+8
N+8
N+8
N+8
6
High-Definition Video Format Converter
D
D
D
D
9
N+9
N+9
N+9
N+9
7
10
D
D
D
D
N+10
N+10
N+10
N+10
8
11
D
D
D
D
N+11
N+11
N+11
N+11
9
12
streaming valid data through the part, a
RESET event should be used to align the
clock edges (see Figure 4 & 5).
Furthermore, RESET will clear HF
HF
rising edge of clock will clear flags HF
and HF
clock. Please note HBLANK should be
From Input Demux
10
F
F
OUTBIAS
Video Imaging Products
IGURE
IGURE
1
From Core
. A LOW state detected on RESET on a
INBIAS
13
0
1
1-0
on the following rising edge of
1-0
8. I
9. O
14
13
2
1
HBLANK Word C
HBLANK Word D
HBLANK Word A
HBLANK Word B
2
NPUT
UTPUT
13
15
R3
2
R3
B
13
IAS
13
16
B
3
03/13/2001–LDS.3370-F
IAS
R0
17
LF3370
R0
13
4
13
0
and
18
0
5
13