lf3370 LOGIC Devices Incorporated, lf3370 Datasheet - Page 12

• Manufacturer Part Number: lf3370
• Description: High-definition Video Format Converter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
output of the LUT section.
LUT address can be chosen from any of
the 4 possible10-bit words that are
‘window’ selected from the13-bit Input
data bus. Configuring the desired LUT
address selector position is accomplished
by programming bits 10 & 9 of Configura-
tion Register 1. Once the LUT Select Data
position is programmed, it is meant to
control all three Gamma LUTs. Therefore,
the address selector positions of the three
LUTs cannot be independently controlled.
LUT loading is discussed in the
Interface™ section.
Rounding
The rounding circuitry found in the Matrix
Multiplier and Half-Band Filter sections
work in the same manner. The truncated
20 MSBs from the Matrix Multiplier or
Half-Band Filter output may be rounded
by being added to the contents of one of the
four Round Registers (see Figure 13). Each
round register is 20 bits wide and user-
programmable. This allows the Matrix
Multiplier’s or Half-Band Filter’s output to
be rounded to any precision required.
RSL
Round Registers are used in each Round-
ing Circuitry. A value of 00 on RSL
selects Round Register 0. A value of 01
selects Round Register 1 and so on. RSL
0
desired. If rounding is not desired, the
user must load and select a Round
Register with value of 0. Round Register
loading is discussed in the LF Interface™
section.
Selecting
The selecting circuitry found in the Matrix
Multiplier and Half-Band Filter sections
work in the same manner. The output
word of the Matrix Multiplier and Half-
Band Filter feeding the RSL circuitry is the
20 MSBs. However, only 13 bits may be
sent to the next section. Therefore, the
Select Register determines which 13-bits
are passed. There are four select registers;
RSL
may be changed every clock cycle if
1-0
1-0
determines which of the four
determines which of the four Select
The Gamma
LF
1-0
1-
Registers are used in each Select Circuitry
(see Table 2). A value of 00 on RSL
selects Select Register 0. A value of 01
selects Select Register 1 and so on. RSL
may be changed every clock cycle if
desired. This allows the 13-bit window to
be changed every clock cycle. Select
Register loading is discussed in the
LF Interface™ section.
Limiting
The Limiting Circuitry found in the Matrix
Multiplier and Half-Band Filter sections
work in the same manner. The Limit
Registers determine the valid range of
output values for each of these two
sections. There are four 13-bit Limit
Registers for each section. RSL
mines which of the four Limit Registers
are used in each Limiting Circuitry (see
Figure 13). A value of 00 on RSL
Limit Register 0. A value of 01 selects
Limit Register 1 and so on.
Each Limit Register contains an upper
and lower limit value. If the value fed to
28 (center)
T
10, 46
11, 45
12, 44
13, 43
14, 42
15, 41
16, 40
17, 39
18, 38
19, 37
20, 36
21, 35
22, 34
23, 33
24, 32
25, 31
26, 30
27, 29
ABLE
TAP
1, 55
2, 54
3, 53
4, 52
5, 51
6, 50
7, 49
8, 48
9, 47
3. H
20-bit (MSB) Filter Out (HEX)
ALF
12
Impulse Response Out (Non-Interpolated Bit Weighing)
-B
High-Definition Video Format Converter
AND
FFB5C
FD6A8
FAF1B
F2BD2
FFE35
002D2
FF508
FEA10
0798D
401BC
00725
00F95
01E59
0393E
28B30
F
1-0
0
0
0
0
0
0
0
0
0
0
0
0
0
ILTER
1-0
deter-
1-0
selects
1-0
I
MPULSE
the Limiting Circuitry is less than the
lower limit, the lower limit value is passed
as the Matrix Multiplier section’s or Half-
Band filter section’s output. If the value
fed to the Limiting Circuitry is greater
than the upper limit, the upper limit value
is passed as the Matrix Multiplier section’s
or Half-Band filter section’s output.
RSL
desired thus allowing the limit range to be
changed every clock cycle. When loading
limit values into the device, the upper limit
must be greater than the lower limit. The
most negative and most positive values
you can load into the Limit Registers are
0FFFH and 1000H. Limit Register loading
is discussed in the LF Interface™ section.
LF Interface™
The LF Interface™ is used to load the
Configuration Registers, Matrix Multi-
plier/Key Scaler Coefficient Banks, Look-
Up Tables, Input/Output Bias registers,
RSL registers, HF
and Horizontal Blanking Levels.
Video Imaging Products
1-0
R
ESPONSE
may be changed every clock cycle if
Decimal Equivalent
0
–0.00226593
–0.01071167
–0.02018738
–0.10360334
0.500846862
–0.0008755
–0.0053558
–0.0394993
0.05935097
and HF
0.0013771
0.0034885
0.0076084
0.0148182
0.0279503
0.3179626
0
0
0
0
0
0
0
0
0
0
0
0
0
1
03/13/2001–LDS.3370-F
Count Values,
LF3370