lf3370 LOGIC Devices Incorporated, lf3370 Datasheet - Page 11

• Manufacturer Part Number: lf3370
• Description: High-definition Video Format Converter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
plier by setting bit 4 in Configuration
Register 0 (see Table 5). The maximum
input and output clock rate this section
can operate at is the CLK rate. The total
internal pipeline latency from the input to
the output of this section (including RSL
circuitry) as shown in Figure 12 is 6 cycles.
To perform interpolation, the input data
rate of this section will be half of CLK rate.
Please note the maximum output data
SLCT
F
F
T
IGURE
IGURE
ABLE
00
01
10
11
1-0
From Core
2. S
RSL
14. F
13. RSL C
–10
–20
–30
–40
–50
–60
–70
–80
1-0
S
F
F
F
F
0
12
16
17
18
19
ELECT
2
S
F
F
F
F
REQUENCY
0
20
15
16
17
18
11
R3
S
F
F
F
F
F
IRCUITRY
10
14
15
16
17
ORMATS
20
ROUND
0.1
F
F
F
F
S
FREQUENCY (NORMALIZED)
13
14
15
16
R
9
S
R0
20
ESPONSE OF
F
F
F
F
S
12
13
14
15
8
0.2
S3
F
F
F
F
S
11
12
13
14
S
7
SELECT
13
rate is the CLK rate. To perform decima-
tion, the output data rate of this section
will be half of the input data rate. One
output sample is obtained for every two
input samples.
Once an impulse is clocked into the Half-
Band Filter section, the 55-value output
response begins after 8 clock cycles and
ends after 62 clock cycles. The pipeline
latency from the input of an impulse to its
F
F
F
F
S
10
11
12
13
F
6
S0
13
0.3
ILTER
F
F
F
S
F
10
11
12
9
S
5
UL3
LL3
F
F
S
F
F
10
11
4
8
9
13
0.4
LIMIT
F
S
F
F
F
11
10
S
3
7
8
9
High-Definition Video Format Converter
UL0
LL0
13
S
F
F
F
F
6
7
8
9
2
0.5
13
S
F
F
F
F
S
1
5
6
7
8
S
F
F
F
F
4
5
6
7
0
corresponding output peak is 35 clock
cycles.
The input/output formats are always in
two’s complement format as shown in
Figure 3.
the Half-Band Filter is halved (due to half
of the input samples being padded with
zeros). A right shifted Select window is
required to maintain an overall filter gain
of 1. It is possible that ringing on the
filter’s output could cause the high order
bit (bit F18 in Figure 3 - Interpolate Filter
Output Bit Weighting) to become HIGH. If
a right shifted Select window is used, this
F18 bit becomes the sign bit of the Selected
window – and the output is erroneously
considered negative. To ensure that no
overflow conditions occur, an internal
Limiter within each Half-Band Filter
monitors its output. During Interpolate
mode, this Limiter clamps the output word
to 3FFFFH (20-bit maximum positive value
value 2) if a positive or negative overflow
occurs respectively. The internal 24-bits of
the Half-Band Filter are truncated to 20-
bits and then passed to the Round section
of the RSL circuitry; see RSL section for
further details.
bypassable by use of programmable
delays (see Bypass Options section for
further details).
Look-Up Table
Three optional programmable Input/
Output 1K x 13-bit LUTs have been
provided for Channels A, B, and C for
various uses such as Gamma Correction.
There are NOT actually two LUTs per
channel as shown in Figures 1 and 2; only
one LUT per channel can be selected for
use at any given time. The latency
through a LUT section is 2 cycles. This
latency is present on the datapath regard-
less of whether the LUT is in use or not.
When using a LUT, the appropriate
addressed value will be passed as an
2) or C0000H (20-bit maximum negative
Video Imaging Products
In Interpolate Mode, the gain of
This section is fully
03/13/2001–LDS.3370-F
LF3370