lf3370 LOGIC Devices Incorporated, lf3370 Datasheet - Page 16

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lf3370

Manufacturer Part Number
lf3370
Description
High-definition Video Format Converter
Manufacturer
LOGIC Devices Incorporated
Datasheet
DEVICES INCORPORATED
T
T
T
T
ABLE
ABLE
ABLE
ABLE
BITS
BITS
BITS
BITS
12-0
12-0
12-0
12-0
12. C
13. C
14. C
15. C
FUNCTION
Channel ‘A’ Blanking Word
FUNCTION
Channel ‘B’ Blanking Word
FUNCTION
Channel ‘C’ Blanking Word
FUNCTION
Channel ‘D’ Blanking Word
ONFIGURATION
ONFIGURATION
ONFIGURATION
ONFIGURATION
R
R
R
R
EGISTER
EGISTER
EGISTER
EGISTER
Channel ‘C’ Blanking Level Word
DESCRIPTION
Channel ‘A’ Blanking Level Word
DESCRIPTION
Channel ‘B’ Blanking Level Word
DESCRIPTION
DESCRIPTION
Channel ‘D’ Blanking Level Word
12 – A
13– A
14 – A
15 – A
DDRESS
DDRESS
DDRESS
DDRESS
208
16
207
209
20A
High-Definition Video Format Converter
programmed to double the length [(de-
sired length x 2) – 2)] to properly align
data due to the core running at half the
CLK rate.
First Operation Select
‘First Operation Select’ is a bypassing
option where you select to use the first
functional block (Half-Band Filter or
Matrix Multiplier/Key Scaler) in any given
arrangement. If the device was arranged in
such a way that the Half-Band Filter section
fed the Matrix Multiplier/Key Scaler section
and ‘First Operation Select’ was enabled,
the Half-Band Filter section will be used
and the Matrix Multiplier/Key Scaler
section will be bypassed.
If the device was arranged in such a way
that the Matrix Multiplier/Key Scaler
section fed the Half-Band Filter section
and ‘First Operation Select’ was enabled,
the Matrix Multiplier/Key Scaler section
will be used - its output will be routed
directly to the output LUT section. Unlike
in other bypassing options , the total
pipeline latency of the LF3370 is reduced
by the appropriate delay. If the Half-Band
Filter section was bypassed by this method,
the overall pipeline latency should be
reduced by 35 CLK cycles. If the Matrix
Multiplier section was bypassed by this
method, the overall pipeline latency
should be reduced by 6 CLK cycles. This
function is implemented by configuring bit
9 of Configuration Register 0. The ‘Func-
tional Arrangement’ of the device is
determined by configuring bit 4 of Con-
figuration Register 0.
Video Imaging Products
03/13/2001–LDS.3370-F
LF3370

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