lf3324 LOGIC Devices Incorporated, lf3324 Datasheet - Page 4

• Manufacturer Part Number: lf3324
• Description: 24mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
LOGIC Devices Incorporated
Operating Modes
Asynchronous FIFO mode (OPMODE = 3)
In OPMODE 3, the LF3324 is configured as asynchronous First-In-First-Out 24Mbit memory, with indepen-
dent read and write clocks to allow for asynchronous operation. This mode is ideal for buffering or burst
data applications. Arbitrary write/read pointer jumping is supported in all FIFO modes. In this mode the
device can re-time a data stream according to a read sync signal (RSET or RCLR) and either ITU-R656
Timing Reference Signals (TRS) embedded within the incoming (video) data or the falling edge of a write
sync signal applied to WCLR, WSET, or MARK.
core may fill or empty if they differ in average frequency. After it “fills,” the LF3324 continues writing and
the oldest data gets written over. If the memory core “empties” (and neither the read nor write pointer
have been set or cleared during run-time) the read pointer stops incrementing, and the device re-reads the
last written sample until more data is written. In either case, when the read and write addresses are the
same, the COLLIDE flag will go high, to alert the host. The almost-full (PF) and almost-empty (PE) flags
provide advance warning of these conditions whenever user-selected “fullness” or “emptiness” thresholds,
expressed in approximate eightieths of the memory core size, are exceeded. For example, if the 1/80 and
79/80 thresholds are enabled, flag PE will go HIGH whenever the read pointer lags behind the write pointer
by less than 1/80 of the memory space, and flag PF will go HIGH whenever the read pointer leads the
write pointer by this amount. (Calculations are performed modulo the total address space.) The data input
and output are sequential and the timing between write and read sync signals dynamically determines the
effective delay (depth) of the FIFO.
The “stop reading when empty” FIFO-mode behavior can be avoided by making sure LOAD is HIGH and
issuing any write or read pointer SET or CLEAR command at any time. This effectively gets the device out
of this “read-pointer-halting” mode from that point onwards, but invalidates the flags. Random Access Mode
allows free manipulation of the r/w pointers, and never halts the read pointer without being commanded
to do so using REN. Since Random Access mode naturally increments the r/w pointers sequentially, like
in FIFO mode, it may be a better mode to use if complex pointer manipulation of a single-channel of
memory is desired.
Synchronous shift register mode (OPMODE = 0)
In OPMODE 0, the LF3324 becomes a shift register with programmable total latency up to 2
cycles. Writes and reads occur simultaneously, hence synchronous operation.
In OPMODE 0, the user provides a single clock for both the input and output clocks and specifies a desired
input-to-output data path latency, configuration register “WADDR” via the control interface. WCLK and RCLK
must be tied together, as should WEN and REN. When activated, WADDR will begin to countdown, and
once expired, will allow the inputs to begin to appear on the outputs. In OPMODE 0, WADDR countdown
can be activated in two ways. The first occurs when the first enable is brought LOW after the LOAD
signal has been set HIGH after MPU programming. The second is by bringing LOAD HIGH once MPU
programming complete, after the enables have been brought LOW.
Random Access Mode (OPMODE = 1)
Random Access mode is a FIFO mode, with the capability of either full-time write or read pointer Random
Accessability. This mode also supports write and read pointer jumps to arbitrary locations throughout
the address space. Unlike Asynchronous FIFO mode, Random Access mode does not disable memory
reads when the read pointer catches up to the write pointer. Write pointer manipulation can be done
The input (write) and output (read) clocks need not be synchronous with one another, although the memory
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24Mbit Frame Buffer / FIFO
Preliminary Datasheet
Video Imaging Product
June 8, 2007 LDS.3324 G
24
-8 clock
LF3324