lf3324 LOGIC Devices Incorporated, lf3324 Datasheet - Page 12

• Manufacturer Part Number: lf3324
• Description: 24mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
Data Outputs
LOGIC Devices Incorporated
Detailed Signal Definitions
REN - Read Enable
If REN is LOW and the output port is enabled, data is read and presented on Q[11:0] after t
from the rising edge of RCLK. If REN goes HIGH, the last value loaded into output register will remain
unchanged and the read pointer will be held. The user must anticipate the use of REN by one cycle.
Therefore when desiring not to read a sample, REN must be brought high the cycle before.
PROGRAM - Serial/Parallel Interface Selector
When the user wishes to use the serial microprocessor to configure the LF3324, the PROGRAM pin must
be set LOW. If the user wishes to use the parallel interface, PROGRAM must be set HIGH.
LOAD – Instruction Load
Bringing asynchronous control LOAD LOW updates the working instruction latches to match the current
contents of the instruction preload latches. Holding it LOW causes the working latches to reflect all ongoing
instruction preloads. Holding it HIGH permits the user to preset the instruction preload latches to any
desired configuration without disturbing the work in progress. After any write to the configuration registers,
LOAD must be brought high for one cycle, and can then be brought and left low if so desired.
RESET - Global Reset
Bringing synchronous control RESET LOW forces all state machines and read and write pointers to 0 and
holds them there until it is released HIGH. It also forces the configuration registers to their default states,
if and only if LOAD is also LOW. The user may then modify the control registers as necessary. Bringing
RESET LOW while holding LOAD HIGH will reset the state machines and pointers, but will not change
either the preload or the working latches.
OE - Output Enable
When OE is LOW, Q[11:0] is enabled for output. When OE is HIGH, Q[11:0] is placed in a high-impedance
state. In 10-bit modes, Q1-0 are unconditionally tristated. In 8-bit modes, Q3-0 are tristated. The flag
outputs are not affected by OE.
PCE
When LOW, PCE
enables writing to die 1 with the parallel micrprocessor interface.
PWE - Parallel Interface Write Enable
When LOW, PWE enables writing to the LF3324’s Instruction Registers with the parallel micrprocessor
interface.
PRE - Parallel Interface Read Enable
When LOW, PRE enables reading from the LF3324’s Instruction Registers with the parallel micrprocessor
interface.
Q
Q[11:0] is the 12-bit registered data output port. Q[11:0] is always the MSB. In 10-bit mode, bits
1 and 0 are tristated. In 8-bit mode, bits 3-0 are tristated. All active bits are updated on each
rising edge of RCLK when REN is LOW.
11-0
0
- Data Output
/PCE
1
- Parallel Interface Chip Enable
0
enables writing to die 0 with the parallel micrprocessor interface. When LOW, PCE
12
24Mbit Frame Buffer / FIFO
Preliminary Datasheet
Video Imaging Product
June 8, 2007 LDS.3324 G
D
has elapsed
LF3324
1