lf3324 LOGIC Devices Incorporated, lf3324 Datasheet - Page 24

• Manufacturer Part Number: lf3324
• Description: 24mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

Write Reset Timing
Read Reset Timing
Random Access Read Pointer ‘Jump’ Timing
DEVICES INCORPORATED
LOGIC Devices Incorporated
ADDR
WEN = LOW
CLR and SET both programmed to be falling edge sensitive
*
*
Q[11:0]
D[11:0]
Rising Edge 4: Sets Write Pointer to Address A (based on WADDR) and latches data on D to be written in Address A
Q[11:0]
WCLR
Rising Edge 1: Clears Write Pointer and latches data on D to be written in address 0
WCLK
WSET
RCLK
RCLK
RSET
CLR
REN = LOW
NOTE: CLR programmed as being falling edge sensitive
It takes 9 REN-enabled rising edges of RCLK (including the edge that latches a LOW on CLR) to pass the contents of address 0 to the Q port.
23-0
OE = LOW
NOTE: RSET programmed to be falling edge sensitive
NOTE: It takes 14 rising edges of RCLK upon setting/jumping the Read pointer
(to the 24bit Address "A" on ADDR) for the contents of location A to be dumped onto Q
(n)
t
D
REN = LOW WADDRSEL= LOW RADDRSEL= HIGH OPMODE[2:0]=001 MARK_SEL (Register 9[3]) =1
(n–2)
t
RWS
(n+1)
(n)
1
t
RWH
(n-1)
t
DS
A
23–0
t
t
1
DH
RWS
t
(n+1)
DS
(0)
2
1
t
DH
(n)
(n+2)
(1)
2
24
....
13
(n+13)
(2)
3
8
t
14
RWH
t
D
t
(A)
RWS
(n+8)
(A)
4
9
24Mbit Frame Buffer / FIFO
t
D
(A+1)
Preliminary Datasheet
(A+1)
(0)
Video Imaging Product
5
10
June 8, 2007 LDS.3324 G
(1)
LF3324