lf3324 LOGIC Devices Incorporated, lf3324 Datasheet - Page 28

• Manufacturer Part Number: lf3324
• Description: 24mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

Speed
The information contained herein is subject to change without notice. LOGIC Devices reserves the right to make changes to or discontinue any semiconductor product or service
without notice. LOGIC Devices assumes no responsibility for the use of any circuitry other than circuitry embodied in a LOGIC Devices product. Nor does it convey or imply any license
under patent or other rights. LOGIC Devices products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless
pursuant to an express written agreement with LOGIC Devices. Furthermore, LOGIC Devices does not authorize its products for use as critical components in life-support systems
where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of LOGIC Devices’ products in life-support system applications implies
that the manufacturer assumes all risk of such use and in doing so indemnifies LOGIC Devices against all charges.
_
DEVICES INCORPORATED
LOGIC Devices Incorporated
Package and Ordering Information
0°C to 70°C--Commercial Screening
ADDR
ADDR
ADDR
ADDR
ADDR
OE_b
VCCI
14
Q
Q
Q
Q
Q
PE
Q
10
11
5
3
0
8
12
15
17
20
23
ADDR
ADDR
ADDR
ADDR
REN_b
VCCO
VCCO
VCCO
13
RCLK
VCCI
VCCI
Q
Q
PF
9
4
14
16
21
22
1.00 REF
172 Ball - Low Profile Ball Grid Array (LBGA)
COLLIDE WADRSEL
RSET_b
ADDR
ADDR
VCC
GNDO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCI
12
Q
Q
7
1
INT
13
18
PADDR
RCLR_b
ADDR
WSET_b
VCC
GNDO
GNDO
GNDO
GNDO
GNDO
GNDO
VCCO
VCCI
11
INT
19
5
WMARK_b RADRSEL
WCLR_b
PADDR
PADDR
PADDR
GND
GNDO
GNDO
VCCO
VCCI
10
Q
Q
6
2
INT
3
4
2
Notes:
PADDR
PADDR
LOAD_b
GND
VCC
GNDO
GNDO
VCCO
VCCO
9
INT
INT
VCC
VCCO = 3.3V
VCCI = 3.3V
Ground
LF3324BGC
0
1
PROGRAM
INT
VCC
GND
PDATA
GNDO
PCE
SDA
SCL
8
= 1.8V
INT
INT
0
7
28
CHIP_ID
VCC
PDATA
GNDO
PDATA
PWEB
PREB
VCCO
7
INT
6
5
6
CHIP_ID
CHIP_ID
CHIP_ID
GND
GND
PDATA
PDATA
GNDO
GNDO
VCCO
6
INT
INT
4
3
5
4
3
CHIP_ID
CHIP_ID
GND
GND
GND
PDATA
PDATA
VCC
PDATA
VCCO
PCE
5
D
6
INT
INT
INT
INT
1
2
0
1
2
1
WIEN_b
VCC
VCC
GND
GND
GND
GND
GND
TRST_b
ADDR
ADDR
TMS
TCK
D
4
3
INT
INT
INT
INT
INT
INT
INT
3
6
GND
ADDR
VCC
WEN_b
VCC
VCC
VCC
ADDR
ADDR
TDI
TDO
3
D
D
D
8
4
0
BALL PAD CORNER
INT
INT
INT
INT
INT
11
1
8
RESET_b
24Mbit Frame Buffer / FIFO
VCC
ADDR
ADDR
ADDR
GNDO
VCCO
VCCI
VCCI
VCCI
VCCI
VCCI
2
D
D
9
1
INT
0
5
9
1.00 REF
ADDR
GND
VCC
ADDR
ADDR
ADDR
VCC
GND
WCLK
1
D
D
D
D
D
Preliminary Datasheet
11
10
7
5
2
INT
INT
INT
INT
10
2
4
7
Video Imaging Product
A
B
C
D
E
F
G
H
J
K
L
M
N
P
June 8, 2007 LDS.3324 G
LF3324