lf3324 LOGIC Devices Incorporated, lf3324 Datasheet - Page 17

• Manufacturer Part Number: lf3324
• Description: 24mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
LOGIC Devices Incorporated
Configuration Register Definitions
Register 8[2:0] = OPMODE[2:0] - operating mode
000
001
010
011
1XX
Register 9[7:6] = TRS_SYNC[1:0] - response to embedded TRS EAV
00
01
10
11
Register 9[4] = FLD frame/field sync select
0
1
Register 9[3] MARK_SEL - This signal is used in combination with pin RADRSEL to determine to
effect of bringing RSET low on the read pointer(s). When RSET goes to 0:
0
1
force read pointer(s) to marked address(es) (default)
force read pointer(s) as shown in following table:
disable TRS sync detection (default)
F-bit of embedded TRS EAV marks current write pointer.
F-bit of embedded TRS EAV sets current write pointer to value
set by ADDR[23:0] or WADDR
RESERVED
use only falling F-bit in EAV (frame-based sync); ignore rising F-bit (default)
use both rising and falling F-bit in EAV (field-based sync)
RADRSEL
1
0
RESERVED
Random Access
RESERVED
FIFO
RESERVED
17
Read Pointer Equals:
ADDR[23:0] address
RADDR address
24Mbit Frame Buffer / FIFO
Preliminary Datasheet
Video Imaging Product
June 8, 2007 LDS.3324 G
LF3324