lf3324 LOGIC Devices Incorporated, lf3324 Datasheet - Page 16

• Manufacturer Part Number: lf3324
• Description: 24mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
LOGIC Devices Incorporated
Configuration Register Definitions
Register 0[3:0], Register 1[7:0] = ROW_LENGTH[11:0] - for Cartesian-to-linear address map
This control governs the remapping of Cartesian coordinates arriving on ADDR[11-0] (horizontal/column
component) and ADDR[23-12] (vertical/row component) into a linear address, for use by the chip’s internal
address generator. Setting ROW_LENGTH to 0 causes the incoming address to be interpreted directly as a
linear address, with the 24bits ADDR[23:0] address.
Register 2[7:0], Register 3[7:0], Register 4[7:0] = WADDR[23:0] - 24bit ‘Jump’ Address
Configuration register WADDR defines a static 24bit address (image pixel or memory location) that
the Write pointer can be ‘jumped’ to. Bringing WSET LOW forces/jumps the memory write pointer to
the address defined by WADDR (when WADRSEL is LOW). When used in this way, WADDR is an
override address. For 2-D applications, where ROW_LENGTH defines a frame’s Horizontal dimension,
, WADDR[11:0] is equal to the 12-bit X-coordinate (Horizontal) and WADDR[23:12] is considered the
Y-coordinate (Vertical) in a Cartesian Coordinate system. When ROW_LENGTH is 0, WADDR[23:0]
is considered to be a linear address in the memory space. By changing the ROW_LENGTH, the
X-coordinate can be from 0 to (ROW_LENGTH-1) to make up the Cartesian plane. For example, if
ROW_LENGTH = 16, the X-coordinate or WADDR[11:0] can be from 0 to 15 in the Cartesian space.
Register 5[7:0], Register 6[7:0], Register 7[7:0] = RADDR[23:0] - 24bit ‘Jump’ Address
Bringing RSET LOW forces/jumps the read pointer to the address defined by RADDR.
Register 8[7:6] = WIDTH[1:0] - data word size at input/output ports
0x
10
11
Register 8[5:4] = Reserved
Register 8[3] = MARK_ACTIVE_RSET
0
1
8 bits
10 bits
12 bits
ignores the internal RSET that occurs following the MARK
obeys the internal RSET according to the MARK
Input Port
D[11:4]
D[11:2] (default)
D[11:0]
16
Output Port
Q[11:4] (Q[3:0] tristated)
Q[11:2] (Q[1:0] tristated)
Q[11:0]
24Mbit Frame Buffer / FIFO
Preliminary Datasheet
Video Imaging Product
June 8, 2007 LDS.3324 G
LF3324