mc9s12uf32 Freescale Semiconductor, Inc, mc9s12uf32 Datasheet - Page 60

• Manufacturer Part Number: mc9s12uf32
• Description: System Chip Guide V01.05
• Manufacturer: Freescale Semiconductor, Inc

System on a Chip Guide — 9S12UF32DGV1/D V01.05
2.4.21 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 / Low-Byte Strobe (LSTRB)
PE3 can be used as a general-purpose I/O in all modes and is an input with an active pull-up out of reset.
PE3 can also be configured as a Low-Byte Strobe (LSTRB). The LSTRB signal is used in write operations,
so external low byte writes will not be possible until this function is enabled. LSTRB can be enabled by
setting the LSTRE bit in the PEAR register. In Expanded Wide and Emulation Narrow modes, and when
BDM tagging is enabled, the LSTRB function is multiplexed with the TAGLO function. When enabled a
logic zero on the TAGLO pin at the falling edge of ECLK will tag the low byte of an instruction word
being read into the instruction queue.
2.4.22 PE2 / R/W — Port E I/O Pin 2 / Read/Write
PE2 can be used as a general-purpose I/O in all modes and is configured an input with an active pull-up
out of reset. If the read/write function is required it should be enabled by setting the RDWE bit in the PEAR
register. External writes will not be possible until the read/write function is enabled.
2.4.23 PE1 / IRQ — Port E input Pin 1 / Maskable Interrupt Pin
PE1 is always an input and can always be read. The PE1 pin is also the IRQ input used for requesting an
asynchronous interrupt to the MCU. During reset, the I bit in the condition code register (CCR) is set and
any IRQ interrupt is masked until software enables it by clearing the I bit. The IRQ is software
programmable to either falling edge-sensitive triggering or level-sensitive triggering based on the setting
of the IRQE bit in the IRQCR register. The IRQ is always enabled and configured to level-sensitive
triggering out of reset. It can be disabled by clearing IRQEN bit in the IRQCR register. There is an active
pull-up on this pin while in reset and immediately out of reset. The pull-up can be turned off by clearing
PUPEE in the PUCR register.
2.4.24 PE0 / XIRQ — Port E input Pin 0 / Non Maskable Interrupt Pin
PE0 is always an input and can always be read. The PE0 pin is also the XIRQ input for requesting a
non-maskable asynchronous interrupt to the MCU. During reset, the X bit in the condition code register
(CCR) is set and any XIRQ interrupt is masked until MCU software enables it by clearing the X bit.
Because the XIRQ input is level sensitive triggered, it can be connected to a multiple-source wired-OR
network. There is an active pull-up on this pin while in reset and immediately out of reset. The pull-up can
be turned off by clearing PUPEE in the PUCR register.
2.4.25 PJ2 / MSSCLK/ROMCTL - Port J I/O Pin 2
PJ2 is a general purpose input or output pin. In expanded modes the PJ2 pin can be used to determine the
reset state of the ROMON bit in the MISC register. At the rising edge of RESET, the state of the PJ2 pin
is latched to the ROMON bit. When the MSHC module is enabled it becomes the serial clock line
(MSSCLK) for the MSHC module. While in reset and immediately out of reset the PJ2 pin is configured
as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9UF32 Block Guide and
the MSHC Block Guide for information about pin configurations.
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