mc9s12uf32 Freescale Semiconductor, Inc, mc9s12uf32 Datasheet - Page 55

• Manufacturer Part Number: mc9s12uf32
• Description: System Chip Guide V01.05
• Manufacturer: Freescale Semiconductor, Inc

Pin Name
Function
Freescale Semiconductor
PB[7:0]
RESET
REF3V
BKGD
RREF
DMH
DMF
PJ2
RPU
DPF
DPH
PM4
PM3
PQ7
PQ6
PQ5
PA0
PJ0
PJ1
1
2
Pin Name
ADDR[7:0]/
Function
DATA[7:0]
ADDR8/
DATA8
MODC
SDAT7
SDAT6
SDAT5
SALE
SCLE
SBSY
SWP
SCE
—
—
—
—
—
—
—
—
2
Pin Name
CFINPACK
Function
CFIOIS16
CFD[7:0]
CFIORW
CFCE1
CFCE2
TAGHI
CFD8
CFA7
CFA6
CFA5
—
—
—
—
—
—
—
—
3
Pin Name
Function
ATAD[7:0]
ATAIOWR
SDDATA2
SDDATA1
ATACS0
ATACS1
ATAD8
IOC7
IOC6
IOC5
—
—
—
—
—
—
—
—
—
4
Pin Name
Function
SDCMD
IOC[7:0]
SDCMD
SDCLK
IOC3
IOC2
—
—
—
—
—
—
—
—
—
—
—
—
—
5
System on a Chip Guide — 9S12UF32DGV1/D V01.05
Supply
VDD3X
VDD3X
VDD3X
VDD3X
VDD3X
VDD3X
VDD3X
VDD3X
VDDR
VDDR
VDDR
VDDX
VDDX
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
Rail
CTRL
Always
PERM/
PERM/
PERQ/
PERQ/
PERQ/
PUCR Disabled
PUCR Disabled
PERJ/
PERJ/
PERJ/
PPSM
PPSM
PPSQ
PPSQ
PPSQ
PPSJ
PPSJ
PPSJ
Internal Pull
NA
NA
NA
NA
NA
NA
NA
NA
up
Resistor
Reset
State
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
NA
NA
NA
NA
NA
NA
NA
NA
Up
Port A I/O pin; multiplexed
address/data; CFHC Data;
ATA5HC Data; SDHC SDCMD
signal.
Port B I/O pin; multiplexed
address/data; CFHC Data;
ATA5HC Data; Timer channels
External reset pin
Background debug; mode pin;
tag signal high
USB D+ pull up resistor
termination
External bias resistor
USB full speed D+ data line
USB high speed D+ data line
USB full speed D- data line
USB high speed D- data line
3.3V regulator reference for
driving external NMOS regulator,
default output 0V
Port J I/O Pin; SMHC SALE
signal; CFHC IOWR signal;
ATA5HC IOWR signal.
Port J I/O Pin; SMHC SCLE
signal; CFHC CE1 signal;
ATA5HC CS0 signal.
Port J I/O Pin; SMHC SWP
signal; CFHC CE2 signal;
ATA5HC CS1 signal.
Port M I/O Pin; SMHC SBSY
signal; SDHC data line; CFHC
CFIOIS16 signal; Timer
Channel.
Port M I/O Pin; SMHC SCE
signal; SDHC data line; CFHC
CFINPACK signal, Timer
Channel.
Port Q I/O Pins; SMHC Data
line; CFHC address line; Timer
channel
Port Q I/O Pins; SMHC Data
line; CFHC address line; Timer
channel; SDHC Clock signal.
Port Q I/O Pins; SMHC Data
line; CFHC address line; Timer
channel; SDHC Command
signal.
Description
55