mc9s12uf32 Freescale Semiconductor, Inc, mc9s12uf32 Datasheet - Page 59

• Manufacturer Part Number: mc9s12uf32
• Description: System Chip Guide V01.05
• Manufacturer: Freescale Semiconductor, Inc

System on a Chip Guide — 9S12UF32DGV1/D V01.05
I/O Pins
PA[7:0] are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus. In single chip mode, this port can be configured as
data bus for CFHC or ATA5HC. Refer to CFHC and ATA5HC block guide for further information.
2.4.16 PB[7:0] / ADDR[7:0] / DATA[7:0] / CFD[7:0] / ATAD[7:0] — Port B I/O
Pins
PB[7:0] are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus. In single chip mode, this port can be configured as
data bus for CFHC or ATA5HC. Refer to CFHC and ATA5HC block guide for further information.
2.4.17 PE7 / NOACC — Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC
signal, when enabled, is used to indicate that the current bus cycle is an unused or free cycle. This signal
will assert when the CPU is not using the bus.
2.4.18 PE6 / MODB / IPIPE1 — Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active
when RESET is low.
2.4.19 PE5 / MODA / IPIPE0 — Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active
when RESET is low.
2.4.20 PE4 / ECLK— Port E I/O Pin 4 / E-Clock Output
PE4 is a general purpose input or output pin. It can also be configured as the output connection for the
internal bus clock (ECLK). ECLK is used to demultiplex the address and data in expanded modes and is
used as a timing reference. The ECLK frequency is equal to 1/2 the crystal frequency out of reset. The
ECLK output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in
the MODE register and the ESTR bit in the EBICTL register. All clocks, including the ECLK, are halted
when the MCU is in STOP mode. It is possible to configure the MCU to interface to slow external
memory. ECLK can be stretched for such accesses. The PE4 pin is initially configured as ECLK output
with stretch in all expanded modes. Reference the MISC register (EXSTR[1:0] bits) for more information.
In normal expanded narrow mode, the ECLK is available for use in external select decode logic or as a
constant speed clock for use in the external application system.
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