mc9s08qg4 Freescale Semiconductor, Inc, mc9s08qg4 Datasheet - Page 221

• Manufacturer Part Number: mc9s08qg4
• Description: Hcs08 Microcontrollers Microcontroller Family
• Manufacturer: Freescale Semiconductor, Inc

15.4.3
This register is used to set the prescaler and bit rate divisor for an SPI master. This register may be read or
written at any time.
Freescale Semiconductor
SPPR[2:0]
MODFEN
BIDIROE
SPISWAI
SPR[2:0]
Reset
SPC0
Field
Field
6:4
2:0
4
3
1
0
W
R
SPI Baud Rate Register (SPIBR)
Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or
effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer
to
0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
Bidirectional Mode Output Enable — When bidirectional mode is enabled by SPI pin control 0 (SPC0) = 1,
BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin.
Depending on whether the SPI is configured as a master or a slave, it uses either the MOSI (MOMI) or MISO
(SISO) pin, respectively, as the single SPI data I/O pin. When SPC0 = 0, BIDIROE has no meaning or effect.
0 Output driver disabled so SPI data I/O pin acts as an input
1 SPI I/O pin enabled as an output
SPI Stop in Wait Mode
0 SPI clocks continue to operate in wait mode
1 SPI clocks stop when the MCU enters wait mode
SPI Pin Control 0 — The SPC0 bit chooses single-wire bidirectional mode. If MSTR = 0 (slave mode), the SPI
uses the MISO (SISO) pin for bidirectional SPI data transfers. If MSTR = 1 (master mode), the SPI uses the
MOSI (MOMI) pin for bidirectional SPI data transfers. When SPC0 = 1, BIDIROE is used to enable or disable the
output driver for the single bidirectional SPI I/O pin.
0 SPI uses separate pins for data input and data output
1 SPI configured for single-wire bidirectional operation
SPI Baud Rate Prescale Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate prescaler
as shown in
drives the input of the SPI baud rate divider (see
SPI Baud Rate Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in
Table
divider is the SPI bit rate clock for master mode.
0
0
7
Table 15-2
15-6. The input to this divider comes from the SPI baud rate prescaler (see
= Unimplemented or Reserved
Table
SPPR2
for more details).
0
6
15-5. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler
Table 15-4. SPIBR Register Field Descriptions
Table 15-3. SPIC2 Register Field Descriptions
Figure 15-7. SPI Baud Rate Register (SPIBR)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 4
SPPR1
0
5
SPPR0
0
4
Figure
Description
Description
15-4).
3
0
0
Chapter 15 Serial Peripheral Interface (S08SPIV3)
SPR2
0
2
Figure
15-4). The output of this
SPR1
0
1
SPR0
0
0
221