mc9s08qg4 Freescale Semiconductor, Inc, mc9s08qg4 Datasheet - Page 189

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mc9s08qg4

Manufacturer Part Number
mc9s08qg4
Description
Hcs08 Microcontrollers Microcontroller Family
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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13.3.2
MTIMCLK contains the clock select bits (CLKS) and the prescaler select bits (PS).
Freescale Semiconductor
CLKS
Field
7:6
5:4
3:0
PS
Reset:
W
R
Unused register bits, always read 0.
Clock Source Select — These two read/write bits select one of four different clock sources as the input to the
MTIM prescaler. Changing the clock source while the counter is active does not clear the counter. The count
continues with the new clock source. Reset clears CLKS to 000.
00
01
10
11
All other encodings default to the bus clock (BUSCLK).
Clock Source Prescaler — These four read/write bits select one of nine outputs from the 8-bit prescaler.
Changing the prescaler value while the counter is active does not clear the counter. The count continues with the
new prescaler value. Reset clears PS to 0000.
0000 Encoding 0. MTIM clock source ÷ 1
0001 Encoding 1. MTIM clock source ÷ 2
0010 Encoding 2. MTIM clock source ÷ 4
0011 Encoding 3. MTIM clock source ÷ 8
0100 Encoding 4. MTIM clock source ÷ 16
0101 Encoding 5. MTIM clock source ÷ 32
0110 Encoding 6. MTIM clock source ÷ 64
0111 Encoding 7. MTIM clock source ÷ 128
1000 Encoding 8. MTIM clock source ÷ 256
All other encodings default to MTIM clock source ÷ 256.
MTIM Clock Configuration Register (MTIMCLK)
Encoding 0. Bus clock (BUSCLK)
Encoding 1. Fixed-frequency clock (XCLK)
Encoding 3. External source (TCLK pin), falling edge
Encoding 4. External source (TCLK pin), rising edge
7
0
0
Table 13-3. MTIM Clock Configuration Register Field Description
Figure 13-5. MTIM Clock Configuration Register
0
0
6
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 4
0
5
CLKS
0
4
Description
0
3
Chapter 13 Modulo Timer (S08MTIMV1)
0
2
PS
0
1
0
0
189

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