mc9s08rd60fj Freescale Semiconductor, Inc, mc9s08rd60fj Datasheet - Page 198

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mc9s08rd60fj

Manufacturer Part Number
mc9s08rd60fj
Description
Hcs08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Development Support
ENBDM — Enable BDM (Permit Active Background Mode)
BDMACT — Background Mode Active Status
BKPTEN — BDC Breakpoint Enable
FTS — Force/Tag Select
CLKSW — Select Source for BDC Communications Clock
198
Typically, this bit is written to 1 by the debug host shortly after the beginning of a debug session or
whenever the debug host resets the target and remains 1 until a normal reset clears it.
This is a read-only status bit.
If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select) control bit and
BDCBKPT match register are ignored.
When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the BDCBKPT
match register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register
causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction
queue, the CPU enters active background mode rather than executing the tagged opcode.
CLKSW defaults to 0, which selects the alternate BDC clock source.
1 = BDM can be made active to allow active background mode commands.
0 = BDM cannot be made active (non-intrusive commands still allowed).
1 = BDM active and waiting for serial commands.
0 = BDM not active (user application program running).
1 = BDC breakpoint enabled.
0 = BDC breakpoint disabled.
1 = Breakpoint match forces active background mode at next instruction boundary (address need
0 = Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute
1 = MCU bus clock.
0 = Alternate BDC clock source.
Reset in Active BDM:
not be an opcode).
that instruction.
Normal Reset:
Figure 14-5 BDC Status and Control Register (BDCSCR)
Read:
Write:
ENBDM
Bit 7
0
1
= Unimplemented or Reserved
BDMACT
6
0
1
MC9S08RC/RD/RE/RG
BKPTEN
5
0
0
FTS
4
0
0
CLKSW
3
0
1
WS
2
0
0
Freescale Semiconductor
WSF
1
0
0
Bit 0
DVF
0
0

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