mc9s08rd60fj Freescale Semiconductor, Inc, mc9s08rd60fj Datasheet - Page 159

• Manufacturer Part Number: mc9s08rd60fj
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

RAF — Receiver Active Flag
11.9.6 SCI Control Register 3 (SCI1C3)
R8 — Ninth Data Bit for Receiver
T8 — Ninth Data Bit for Transmitter
TXDIR — TxD1 Pin Direction in Single-Wire Mode
ORIE — Overrun Interrupt Enable
Freescale Semiconductor
RAF is set when the SCI receiver detects the beginning of a valid start bit, and RAF is cleared
automatically when the receiver detects an idle line. This status flag can be used to check whether an
SCI character is being received before instructing the MCU to go to stop mode.
When the SCI is configured for 9-bit data (M = 1), R8 can be thought of as a ninth receive data bit to
the left of the MSB of the buffered data in the SCI1D register. When reading 9-bit data, read R8 before
reading SCI1D because reading SCI1D completes automatic flag clearing sequences that could allow
R8 and SCI1D to be overwritten with new data.
When the SCI is configured for 9-bit data (M = 1), T8 may be thought of as a ninth transmit data bit
to the left of the MSB of the data in the SCI1D register. When writing 9-bit data, the entire 9-bit value
is transferred to the SCI shift register after SCI1D is written so T8 should be written (if it needs to
change from its previous value) before SCI1D is written. If T8 does not need to change in the new
value (such as when it is used to generate mark or space parity), it need not be written each time SCI1D
is written.
When the SCI is configured for single-wire half-duplex operation (LOOPS = RSRC = 1), this bit
determines the direction of data at the TxD1 pin.
This bit enables the overrun flag (OR) to generate hardware interrupt requests.
1 = SCI receiver active (RxD1 input not idle).
0 = SCI receiver idle waiting for a start bit.
1 = TxD1 pin is an output in single-wire mode.
0 = TxD1 pin is an input in single-wire mode.
1 = Hardware interrupt requested when OR = 1.
0 = OR interrupts disabled (use polling).
Reset:
Read:
Write:
Figure 11-11 SCI Control Register 3 (SCI1C3)
Bit 7
R8
0
= Unimplemented or Reserved
T8
6
0
MC9S08RC/RD/RE/RG
TXDIR
5
0
4
0
0
ORIE
SoC Guide — MC9S08RG60/D Rev 1.10
3
0
NEIE
2
0
FEIE
1
0
PEIE
Bit 0
0
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