mc9s08rd60fj Freescale Semiconductor, Inc, mc9s08rd60fj Datasheet - Page 107

• Manufacturer Part Number: mc9s08rd60fj
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

IROPEN — IRO Pin Enable
7.6.3 CMT Modulator Status and Control Register (CMTMSC)
The CMT modulator status and control register (CMTMSC) contains the modulator and carrier generator
enable (MCGEN), end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable
(BASE), extended space (EXSPC), prescaler (CMTDIV1:CMTDIV0) bits, and the end of cycle (EOCF)
status bit.
EOCF — End of Cycle Status Flag
Freescale Semiconductor
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The IROPEN bit is used to enable and disable the IRO pin. When the pin is enabled, it is an output that
drives out either the CMT transmitter output or the state of the IROL bit depending on whether the
MCGEN bit in the CMTMSC register is set. Also, the state of the output is either inverted or not
depending on the state of the CMTPOL bit. When the pin is disabled, it is in a high impedance state so
it doesn’t draw any current. The pin is disabled during reset.
The EOCF bit is set when:
This flag is cleared by a read of the CMTMSC register followed by an access of CMTCMD2 or
CMTCMD4.
In the case where the MCGEN bit is cleared and then set before the end of the modulation cycle, EOCF
will not be set when MCGEN is set, but will be set at the end of the current modulation cycle.
1 = IRO pin enabled as output
0 = IRO pin disabled
The modulator is not currently active and the MCGEN bit is set to begin the initial CMT
transmission.
At the end of each modulation cycle while the MCGEN bit is set. This is recognized when a match
occurs between the contents of the space period register and the down-counter. At this time, the
counter is initialized with the (possibly new) contents of the mark period buffer, CMTCMD1 and
CMTCMD2. The space period register is loaded with the (possibly new) contents of the space
period buffer, CMTCMD3 and CMTCMD4.
1 = End of modulator cycle has occurred
0 = No end of modulation cycle occurrence since flag last cleared
Figure 7-10 CMT Modulator Status and Control Register (CMTMSC)
Reset:
Read:
Write:
EOCF
Bit 7
0
CMTDIV1 CMTDIV0
= Unimplemented
6
0
MC9S08RC/RD/RE/RG
5
0
EXSPC
4
0
BASE
SoC Guide — MC9S08RG60/D Rev 1.10
3
0
FSK
2
0
EOCIE
1
0
MCGEN
Bit 0
0
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