mc9s08rd60fj Freescale Semiconductor, Inc, mc9s08rd60fj Datasheet - Page 184

• Manufacturer Part Number: mc9s08rd60fj
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Development Support
14.2 Features
Features of the background debug controller (BDC) include:
Features of the debug module (DBG) include:
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Single pin for mode selection and background communications
BDC registers are not located in the memory map
SYNC command to determine target communications rate
Non-intrusive commands for memory access
Active background mode commands for CPU register access
GO and TRACE1 commands
BACKGROUND command can wake CPU from stop or wait modes
One hardware address breakpoint built into BDC
Oscillator runs in stop mode, if BDC enabled
COP watchdog disabled while in active background mode
Two trigger comparators:
– Two address + read/write (R/W) or
– One full address + data + R/W
Flexible 8-word by 16-bit FIFO (first-in, first-out) buffer for capture information:
– Change-of-flow addresses or
– Event-only data
Two types of breakpoints:
– Tag breakpoints for instruction opcodes
– Force breakpoints for any address access
Nine trigger modes:
– A-only
– A OR B
– A then B
– A AND B data (full mode)
– A AND NOT B data (full mode)
– Event-only B (store data)
– A then event-only B (store data)
– Inside range (A address B)
– Outside range (address < A or address > B)
MC9S08RC/RD/RE/RG
Freescale Semiconductor