mc9s08rd60fj Freescale Semiconductor, Inc, mc9s08rd60fj Datasheet - Page 188
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mc9s08rd60fj
Manufacturer Part Number
mc9s08rd60fj
Description
Hcs08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S08RD60FJ.pdf
(232 pages)
- Current page: 188 of 232
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Development Support
Figure 14-3
shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is
asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long
enough for the target to recognize it (at least two target BDC cycles). The host must release the low drive
before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of
the bit time. The host should sample the bit level about 10 cycles after it started the bit time.
BDC CLOCK
(TARGET MCU)
HOST DRIVE
HIGH-IMPEDANCE
TO BKGD PIN
TARGET MCU
SPEEDUP PULSE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
PERCEIVED START
OF BIT TIME
R-C RISE
BKGD PIN
10 CYCLES
EARLIEST START
OF NEXT BIT
10 CYCLES
HOST SAMPLES BKGD PIN
Figure 14-3 BDC Target-to-Host Serial Bit Timing (Logic 1)
188
MC9S08RC/RD/RE/RG
Freescale Semiconductor
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