lpc1114fn28/102 NXP Semiconductors, lpc1114fn28/102 Datasheet - Page 79

no-image

lpc1114fn28/102

Manufacturer Part Number
lpc1114fn28/102
Description
32-bit Arm Cortex-m0 Microcontroller; Up To 32 Kb Flash And 8 Kb Sram
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
15. Revision history
Table 26.
LPC1110_11_12_13_14
Product data sheet
Document ID
LPC1110_11_12_13_14 v.6
Modifications:
LPC1111_12_13_14 v.5
Modifications:
LPC1111_12_13_14 v.4
Modifications:
LPC1111_12_13_14 v.3
Modifications:
LPC1111_12_13_14 v.2
Modifications:
Revision history
Release date
20111102
20110622
20110210
20101110
20100818
Parts LPC1112FHI33/202 and LPC1114FHI33/302 added.
Parts LPC1112FDH28/102, LPC1114FDH28/102, LPC1114FN28/102,
LPC1112FDH20/102, LPC1110FD20, LPC1111FDH20/002, LPC1112FD20/102 added.
ADC sampling frequency corrected in Table 7 (Table note 7).
Pull-up level specified in Table 3 to Table 4 and Section 7.7.1.
Parameter T
WWDT for parts LPC111x/102/202/302 added in Section 2 and Section 7.15.
Programmable open-drain mode for parts LPC111x/102/202/302 added in Section 2
and Section 7.12.
Condition for parameter T
Table note 4 of Table 5 updated.
Section 13 added.
Removed PLCC44 package information.
Power consumption graphs added for parts LPC111x/102/202/302 (Figure 13 to
Figure 17).
Parameter V
Typical value for parameter N
I
(minimum) for 2.0 V  V
Section 11.6 “ElectroMagnetic Compatibility (EMC)” added.
Power-up characterization added (Section 10.1 “Power-up ramp conditions”).
Parts LPC111x/102/202/302 added (LPC1100L series).
Power consumption data for parts LPC111x/102/202/302 added in Table 7.
PLL output frequency limited to 100 MHz in Section 7.15.2.
Description of RESET and WAKEUP functions updated in Section 6.
WDT description updated in Section 7.14. The WDT is a 24-bit timer.
Power profiles added to Section 2 and Section 7 for parts LPC111x/102/202/302.
V
t
Deep-sleep mode functionality changed to allow BOD and watchdog oscillator as the
only analog blocks allowed to remain running in Deep-sleep mode (Section 7.15.5.3).
V
Reset state of pins and start logic functionality added in Table 3 to Table 5.
Section 7.16.1 added.
Section “Memory mapping control” removed.
V
Section 9.4 added.
2
DS
C-bus pins configured as standard mode pins, parameter I
ESD
DD
OH
updated for SPI in master mode (Table 17).
range changed to 3.0 V  V
and I
All information provided in this document is subject to legal disclaimers.
limit changed to 6500 V (min) /+6500 V (max) in Table 6.
OH
Rev. 6 — 2 November 2011
cy(clk)
hys
specifications updated for high-drive pins in Table 7.
Data sheet status
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product data sheet
for I
corrected on Table 17.
2
C bus pins: typical value corrected V
DD
stg
 3.6 V.
in Table 5 updated.
endu
DD
added in Table 12 “Flash characteristics”.
 3.6 V in Table 15.
LPC1110/11/12/13/14
-
-
-
-
-
Change notice
32-bit ARM Cortex-M0 microcontroller
LPC1111_12_13_14 v.5
LPC1111_12_13_14 v.4
LPC1111_12_13_14 v.3
LPC1111_12_13_14 v.2
LPC1111_12_13_14 v.1
Supersedes
hys
OL
= 0.05V
changed to 3.5 mA
© NXP B.V. 2011. All rights reserved.
DD
in Table 7.
79 of 84

Related parts for lpc1114fn28/102