lpc1114fn28/102 NXP Semiconductors, lpc1114fn28/102 Datasheet - Page 16

• Manufacturer Part Number: lpc1114fn28/102
• Description: 32-bit Arm Cortex-m0 Microcontroller; Up To 32 Kb Flash And 8 Kb Sram
• Manufacturer: NXP Semiconductors

NXP Semiconductors
[1]
[2]
[3]
[4]
Table 6.
LPC1110_11_12_13_14
Product data sheet
Table 5.
[5]
Symbol
XTALOUT
V
V
Symbol
PIO0_0 to PIO0_11
RESET/PIO0_0
PIO0_1/CLKOUT/
CT32B0_MAT2
PIO0_2/SSEL0/
CT16B0_CAP0
PIO0_3
PIO0_4/SCL
SS
SSA
Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V
no pull-up/down enabled.
See
reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down
mode.
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see
When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
Figure 37
LPC1112 pin description table (TSSOP20 with V
LPC1112/14 pin description table (TSSOP28 and DIP28 packages)
for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to
13
16
6
23
24
25
26
27
[5]
[2]
[3]
[3]
[3]
[4]
Start
logic
input
-
-
-
Start
logic
input
yes
yes
yes
yes
yes
Type Reset
I/O
I
I/O
I/O
O
O
I/O
I/O
I
I/O
I/O
I/O
All information provided in this document is subject to legal disclaimers.
Type
O
I
I
state
[1]
-
-
-
-
-
-
I; PU
I; PU
I; PU
I; PU
I; IA
Rev. 6 — 2 November 2011
Reset
state
[1]
-
-
-
Description
Port 0 — Port 0 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 0 pins depends
on the function selected through the IOCONFIG register block.
RESET — External reset input with 20 ns glitch filter. A LOW-going
pulse as short as 50 ns on this pin resets the device, causing I/O
ports and peripherals to take on their default states, and processor
execution to begin at address 0.
PIO0_0 — General purpose digital input/output pin with 10 ns
glitch filter.
PIO0_1 — General purpose digital input/output pin. A LOW level
on this pin during reset starts the ISP command handler.
CLKOUT — Clockout pin.
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2 — General purpose digital input/output pin.
SSEL0 — Slave Select for SPI0.
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 — General purpose digital input/output pin.
PIO0_4 — General purpose digital input/output pin (open-drain).
SCL — I
only if I
register.
Description
Output from the oscillator amplifier.
Ground.
Analog ground.
DDA
2
C Fast-mode Plus is selected in the I/O configuration
2
C-bus, open-drain clock input/output. High-current sink
and V
SSA
LPC1110/11/12/13/14
pins)
32-bit ARM Cortex-M0 microcontroller
…continued
Figure
DD
© NXP B.V. 2011. All rights reserved.
36).
level ); IA = inactive,
Figure
16 of 84
36).