lpc1114fn28/102 NXP Semiconductors, lpc1114fn28/102 Datasheet - Page 31

• Manufacturer Part Number: lpc1114fn28/102
• Description: 32-bit Arm Cortex-m0 Microcontroller; Up To 32 Kb Flash And 8 Kb Sram
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC1110_11_12_13_14
Product data sheet
7.12.1 Features
7.14.1 Features
7.12 General purpose external event counter/timers
7.13 System tick timer
7.14 Watchdog timer (LPC1100 series, LPC111x/101/201/301)
The LPC1110/11/12/13/14 include two 32-bit counter/timers and two 16-bit counter/timers.
The counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes one capture input to trap the timer value
when an input signal transitions, optionally generating an interrupt.
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
Remark: The watchdog timer without windowed features is available on parts
LPC111x/101/201/301.
The purpose of the watchdog is to reset the microcontroller within a selectable time
period.
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A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
Counter or timer operation.
One capture channel per timer, that can take a snapshot of the timer value when an
input signal transitions. A capture event may also generate an interrupt.
Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 2 November 2011
LPC1110/11/12/13/14
32-bit ARM Cortex-M0 microcontroller
© NXP B.V. 2011. All rights reserved.
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