lpc1114fn28/102 NXP Semiconductors, lpc1114fn28/102 Datasheet - Page 60

• Manufacturer Part Number: lpc1114fn28/102
• Description: 32-bit Arm Cortex-m0 Microcontroller; Up To 32 Kb Flash And 8 Kb Sram
• Manufacturer: NXP Semiconductors

NXP Semiconductors
[1]
[2]
LPC1110_11_12_13_14
Product data sheet
Table 21.
[3]
[4]
Symbol
SPI slave (in SPI mode)
T
t
t
t
t
DS
DH
v(Q)
h(Q)
cy(PCLK)
T
main clock frequency f
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
T
T
T
cy(clk)
amb
cy(clk)
amb
= 40 C to 85 C.
= 25 C; for normal voltage supply range: V
= (SSPCLKDIV  (1 + SCR)  CPSDVSR) / f
= 12  T
Dynamic characteristics of SPI pins in SPI mode
Parameter
PCLK cycle time
data set-up time
data hold time
data output valid time in SPI mode
data output hold time in SPI mode
cy(PCLK)
main
.
Fig 32. SPI master timing in SPI mode
, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),
SCK (CPOL = 0)
SCK (CPOL = 1)
Conditions
in SPI mode
in SPI mode
Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1.
MOSI
MISO
MOSI
MISO
All information provided in this document is subject to legal disclaimers.
DD
Rev. 6 — 2 November 2011
main
= 3.3 V.
DATA VALID
DATA VALID
. The clock cycle time derived from the SPI bit rate T
t
v(Q)
[3][4]
[3][4]
[3][4]
[3][4]
DATA VALID
T
DATA VALID
cy(clk)
Min
20
0
3  T
-
-
t
v(Q)
t
DS
DATA VALID
cy(PCLK)
DATA VALID
LPC1110/11/12/13/14
t
clk(H)
t
t
DH
DS
32-bit ARM Cortex-M0 microcontroller
+ 4
DATA VALID
DATA VALID
Typ
-
-
-
-
-
t
clk(L)
t
DH
t
h(Q)
Max
-
-
-
3  T
2  T
t
cy(PCLK)
cy(PCLK)
h(Q)
cy(clk)
© NXP B.V. 2011. All rights reserved.
is a function of the
+ 11
+ 5
CPHA = 1
CPHA = 0
002aae829
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Unit
ns
ns
ns
ns
ns