atmega3250v-8auatmega325v-8ai ATMEL Corporation, atmega3250v-8auatmega325v-8ai Datasheet - Page 14

• Manufacturer Part Number: atmega3250v-8auatmega325v-8ai
• Description: Atmega3250 8-bit Microcontroller With In-system Programmable Flash
• Manufacturer: ATMEL Corporation

7.8
14
Reset and Interrupt Handling
ATmega325/3250/645/6450
ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Figure 7-4.
Figure 7-5 on page 14
cycle an ALU operation using two register operands is executed, and the result is stored back to
the destination register.
Figure 7-5.
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section
ming” on page 264
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL
bit in the MCU Control Register (MCUCR). Refer to
The Reset Vector can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see
250.
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
Result Write Back
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
for details.
clk
clk
CPU
“Boot Loader Support – Read-While-Write Self-Programming” on page
CPU
shows the internal timing concept for the Register File. In a single clock
T1
T1
“Interrupts” on page 48
T2
T2
“Interrupts” on page
T3
T3
for more information.
“Memory Program-
48. The list also
2570L–AVR–08/07
T4
T4