atmega3250v-8auatmega325v-8ai ATMEL Corporation, atmega3250v-8auatmega325v-8ai Datasheet - Page 125
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atmega3250v-8auatmega325v-8ai
Manufacturer Part Number
atmega3250v-8auatmega325v-8ai
Description
Atmega3250 8-bit Microcontroller With In-system Programmable Flash
Manufacturer
ATMEL Corporation
Datasheet
1.ATMEGA3250V-8AUATMEGA325V-8AI.pdf
(362 pages)
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17.11.3
2570L–AVR–08/07
TCCR1C – Timer/Counter1 Control Register C
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the
TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap-
ture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCR1B is written.
• Bit 4:3 – WGM13:2: Waveform Generation Mode
See TCCR1A Register description.
• Bit 2:0 – CS12:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see
17-10
Table 17-6.
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
• Bit 7 – FOC1A: Force Output Compare for Unit A
• Bit 6 – FOC1B: Force Output Compare for Unit B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode.
However, for ensuring compatibility with future devices, these bits must be set to zero when
TCCR1A is written when operating in a PWM mode. When writing a logical one to the
FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit.
The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the
FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the
COM1x1:0 bits that determine the effect of the forced compare.
Bit
(0x82)
Read/Write
Initial Value
CS12
0
0
0
0
1
1
1
1
and
Figure
CS11
0
0
1
1
0
0
1
1
FOC1A
Clock Select Bit Description
R/W
7
0
17-11.
CS10
FOC1B
0
1
0
1
0
1
0
1
R/W
6
0
Description
No clock source (Timer/Counter stopped).
clk
clk
clk
clk
clk
External clock source on T1 pin. Clock on falling edge.
External clock source on T1 pin. Clock on rising edge.
I/O
I/O
I/O
I/O
I/O
R
5
–
0
/1 (No prescaling)
/8 (From prescaler)
/64 (From prescaler)
/256 (From prescaler)
/1024 (From prescaler)
R
4
–
0
ATmega325/3250/645/6450
R
3
–
0
R
2
–
0
R
1
–
0
R
0
–
0
TCCR1C
Figure
125
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