pic24hj12gp202 Microchip Technology Inc., pic24hj12gp202 Datasheet - Page 49

• Manufacturer Part Number: pic24hj12gp202
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

5.2.1
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) have a relatively long start-up
time. Therefore, one or more of the following conditions
is possible after SYSRST is released:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a
• The PLL has not achieved a lock (if PLL is used).
The device will not begin to execute code until a valid
clock source has been released to the system.
Therefore, the oscillator and PLL start-up delays must
be considered when the Reset delay time must be
known.
5.2.2
If the FSCM is enabled, it begins to monitor the system
clock source when SYSRST is released. If a valid clock
source is not available at this time, the device auto-
matically switches to the FRC oscillator and the user
application can switch to the desired crystal oscillator in
the Trap Service Routine.
© 2007 Microchip Technology Inc.
crystal oscillator is used).
POR AND LONG OSCILLATOR
START-UP TIMES
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
Preliminary
PIC24HJ12GP201/202
5.2.2.1
When the system clock source is provided by a crystal
oscillator and/or the PLL, a short delay, T
matically inserted after the POR and PWRT delay
times. The FSCM does not begin to monitor the system
clock source until this delay expires. The FSCM delay
time is nominally 500 μs and provides additional time
for the oscillator and/or PLL to stabilize. In most cases,
the FSCM delay prevents an oscillator failure trap at a
device Reset when the PWRT is disabled.
5.3
Most of the Special Function Registers (SFRs)
associated with the CPU and peripherals are reset to a
particular value at a device Reset. The SFRs are
grouped by their peripheral or CPU function, and their
Reset values are specified in each section of this
manual. The Reset value for each SFR does not
depend on the type of Reset, with the exception of two
registers:
• The Reset value for the Reset Control register,
• The Reset value for the Oscillator Control register,
RCON, depends on the type of device Reset.
OSCCON, depends on the type of Reset and the
programmed values of the Oscillator
Configuration bits in the FOSC Configuration
register.
Special Function Register Reset
States
FSCM Delay for Crystal and PLL
Clock Sources
DS70282B-page 47
FSCM
, is auto-