pic24hj12gp202 Microchip Technology Inc., pic24hj12gp202 Datasheet - Page 119

• Manufacturer Part Number: pic24hj12gp202
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

12.0
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The PIC24HJ12GP201/202 devices support up to eight
input capture channels.
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
• Simple Capture Event modes:
• Capture timer value on every edge (rising and
FIGURE 12-1:
© 2007 Microchip Technology Inc.
Note:
- Capture timer value on every falling edge of
- Capture timer value on every rising edge of
falling)
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
input at ICx pin
input at ICx pin
ICx Pin
INPUT CAPTURE
This data sheet summarizes the features
of the PIC24HJ12GP201/202 devices. It is
not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
“PIC24H
Please see the Microchip web site
(www.microchip.com)
PIC24H
chapters.
Prescaler
(1, 4, 16)
Counter
3
INPUT CAPTURE BLOCK DIAGRAM
Family
Family
System Bus
ICxCON
ICM<2:0> (ICxCON<2:0>)
ICOV, ICBNE (ICxCON<4:3>)
Mode Select
Reference
Reference
for
Edge Detection Logic
Clock Synchronizer
the
ICxI<1:0>
Manual”.
and
Manual
latest
Preliminary
(in IFSn Register)
Set Flag ICxIF
PIC24HJ12GP201/202
Interrupt
Logic
• Prescaler Capture Event modes:
Each input capture channel can select one of two
16-bit timers (Timer2 or Timer3) for the time base.
The selected timer can use either an internal or
external clock.
Other operational features include:
• Device wake-up from capture pin during CPU
• Interrupt on input capture event
• 4-word FIFO buffer for capture values
• Use of input capture to provide additional sources
- Capture timer value on every 4th rising edge
Sleep and Idle modes
- Interrupt optionally generated after 1, 2, 3 or
of external interrupts
-Capture timer value on every 16th rising
of input at ICx pin
4 buffer locations are filled
edge of input at ICx pin
Logic
FIFO
R/W
From 16-bit Timers
TMR2 TMR3
1
ICxBUF
16
0
DS70282B-page 117
16
ICTMR
(ICxCON<7>)