attiny25v ATMEL Corporation, attiny25v Datasheet - Page 80

• Manufacturer Part Number: attiny25v
• Description: Microcontroller With 2/4/8k Bytes In-system Programmable Flash
• Manufacturer: ATMEL Corporation

11.9
11.9.1
11.9.2
80
Register Description
ATtiny25/45/85
GTCCR – General Timer/Counter Control Register
TCCR0A – Timer/Counter Control Register A
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization Mode. In this mode, the
value written to PSR0 is kept, hence keeping the Prescaler Reset signal asserted. This ensures
that the timer/counter is halted and can be configured without the risk of advancing during con-
figuration. When the TSM bit is written to zero, the PSR0 bit is cleared by hardware, and the
timer/counter start counting.
• Bit 0 – PSR0: Prescaler Reset Timer/Counter0
When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared
immediately by hardware, except if the TSM bit is set.
• Bits 7:6 – COM0A1:0: Compare Match Output A Mode
• Bits 5:4 – COM0B1:0: Compare Match Output B Mode
The COM0A1:0 and COM0B1:0 bits control the behaviour of Output Compare pins OC0A and
OC0B, respectively. If any of the COM0A1:0 bits are set, the OC0A output overrides the normal
port functionality of the I/O pin it is connected to. Similarly, if any of the COM0B1:0 bits are set,
the OC0B output overrides the normal port functionality of the I/O pin it is connected to. How-
ever, note that the Data Direction Register (DDR) bit corresponding to the OC0A and OC0B pins
must be set in order to enable the output driver.
When OC0A/OC0B is connected to the I/O pin, the function of the COM0A1:0/COM0B1:0 bits
depend on the WGM02:0 bit setting.
WGM02:0 bits are set to a normal or CTC mode (non-PWM).
Table 11-2.
Bit
0x2C
Read/Write
Initial Value
Bit
0x2A
Read/Write
Initial Value
COM0A1
COM0B1
0
0
1
1
7
TSM
R/W
0
R/W
7
COM0A1
0
Compare Output Mode, non-PWM Mode
COM0A0
COM0B0
0
1
0
1
6
PWM1B
R
0
6
COM0A0
R/W
0
Description
Normal port operation, OC0A/OC0B disconnected.
Toggle OC0A/OC0B on Compare Match
Clear OC0A/OC0B on Compare Match
Set OC0A/OC0B on Compare Match
5
COM1B1
R
0
5
COM0B1
R/W
0
Table 11-2
4
COM0B0
R/W
0
4
COM1B0
R
0
shows the COM0x1:0 bit functionality when the
3
–
R
0
3
FOC1B
R
0
2
–
R
0
2
FOC1A
R
0
1
WGM01
R/W
0
1
PSR1
R
0
R/W
0
WGM00
0
0
PSR0
R/W
0
2586K–AVR–01/08
TCCR0A
GTCCR