attiny25v ATMEL Corporation, attiny25v Datasheet - Page 101

• Manufacturer Part Number: attiny25v
• Description: Microcontroller With 2/4/8k Bytes In-system Programmable Flash
• Manufacturer: ATMEL Corporation

13.2.1
2586K–AVR–01/08
Timer/Counter1 in PWM Mode
When the PWM mode is selected, Timer/Counter1 and the Output Compare Register A -
OCR1A form an 8-bit, free-running and glitch-free PWM generator with output on the
PB1(OC1A).
When the counter value match the content of OCR1A, the OC1A and output is set or cleared
according to the COM1A1/COM1A0 bits in the Timer/Counter1 Control Register A - TCCR1, as
shown in
Timer/Counter1 acts as an up-counter, counting from $00 up to the value specified in the output
compare register OCR1C, and starting from $00 up again. A compare match with OCR1C will
set an overflow interrupt flag (TOV1) after a synchronization delay following the compare event.
Table 13-1.
Note that in PWM mode, writing to the Output Compare Register OCR1A, the data value is first
transferred to a temporary location. The value is latched into OCR1A when the Timer/Counter
reaches OCR1C. This prevents the occurrence of odd-length PWM pulses (glitches) in the event
of an unsynchronized OCR1A. See
Figure 13-4. Effects of Unsynchronized OCR Latching
During the time between the write and the latch operation, a read from OCR1A will read the con-
tents of the temporary location. This means that the most recently written value always will read
out of OCR1A.
COM1A1
0
0
1
1
Unsynchronized OC1A Latch
Table
Synchronized OC1A Latch
Compare Mode Select in PWM Mode
COM1A0
13-1.
0
1
0
1
Effect on Output Compare Pin
OC1A not connected.
OC1A not connected.
OC1A cleared on compare match. Set when TCNT1 = $00.
OC1A set on compare match. Cleared when TCNT1 = $00.
Figure 13-4
Glitch
for an e xample.
Compare Value changes
Compare Value changes
ATtiny25/45/85
Counter Value
Compare Value
PWM Output OC1A
Counter Value
Compare Value
PWM Output OC1A
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