tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 76

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tmp88fw45afg

Manufacturer Part Number
tmp88fw45afg
Description
8 Bit Microcontroller Tlcs-870/x Series
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
5.10
Port P9 (P97 to P90)
5.10
Table 5-7
Note 1: i = 7 to 0
Note 2: OFDRST shows a reset signal of oscillation frequency detection.
output control register (P9CR). When reset, the P9CR register is initialized to 0, with the P9 port set for input mode.
Also, the output latch (P9DR) is initialized to 0 when reset.
is used to select open-drain or tri-state mode for the port. When reset, the P9ODE register is initialized to 0, with tri-
state mode selected for the port.
the oscillation frequency detection reset and Port P9 becomes high impedance.
Port P9 is an 8-bit input/output port. This port is switched between input and output modes using the P9 port input/
The P9 port contains bit wise programmable open-drain control. The P9 port open-drain control register (P9ODE)
If high frequency oscillation stops or becomes abnormal in NORMAL/IDLE mode, the TMP88FW45AFG generates
P9ODE
Port P9 (P97 to P90)
0
0
0
0
1
1
1
1
P9CR
0
0
1
1
0
0
1
1
Data output
Data input
OFDRST
P9ODEi
OUTEN
P9CRi
STOP
P9DR
0
1
0
1
0
1
0
1
Output latch
D
Data input (by reading instruction)
Q
Figure 5-11 Port P9
Input Data from port (Low)
Input Data from port (Low)
"0" (output latch data)
"1" (output latch data)
Input Data from port
Input Data from port
Input Data from port
Input Data from port
Page 62
Input Data from port (Low)
Input Data from port (Low)
"0" (output latch data)
"1" (output latch data)
Input Data from port
Input Data from port
Input Data from port
Input Data from port
Control input
P9i
TMP88FW45AFG
Output data
Hi-Z
Hi-Z
Hi-Z
Hi-Z
"0"
"1"
"0"
"0"

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