tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 129

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

12.3
12.3.1
12.3.2
12.3.3
pulse width modulation (PWM) output modes.
TimerCounter 4 has four types of operating modes: timer, event counter, programmable divider output (PDO), and
Function
and the TC4DR value is detected, an INTTC4 interrupt is generated and the up-counter is cleared. After being
cleared, the up-counter restarts counting.
and the up-counter is cleared. After being cleared, the up-counter restarts counting at rising edge of the TC4 pin.
Since a match is detected at the falling edge of the input pulse to the TC4 pin, the INTTC4 interrupt request is
generated at the falling edge immediately after the up-counter reaches the value set in TC4DR.
machine cycles is required for high- and low-going pulses.
with the internal clock.
PDO4 pin is switched to the opposite state and INTTC4 interrupt request is generated. The up-counter is cleared
at this time and then counting is continued. When a match between the up-counter and the TC4DR value is
detected, the logic level output from the PDO4 pin is switched to the opposite state again and INTTC4 interrupt
request is generated. The up-counter is cleared at this time, and then counting and PDO are continued.
In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter
In the event counter mode, the up-counter counts up at the rising edge of the input pulse to the TC4 pin.
When a match between the up-counter and the TC4DR value is detected, an INTTC4 interrupt is generated
The minimum pulse width applied to the TC4 pin are shown in Table 12-2. The pulse width larger than two
The programmable divider output (PDO) mode is used to generated a pulse with a 50% duty cycle by counting
When a match between the up-counter and the TC4DR value is detected, the logic level output from the
Timer Mode
Event Counter Mode
Programmable Divider Output (PDO) Mode
Note:The event counter mode can used in the NORMAL and IDLE modes only.
Table 12-1 Internal Source Clock for TimerCounter 4 (Example: fc = 20 MHz)
TC4CK
000
001
010
011
Table 12-2 External Source Clock for TimerCounter 4
Resolution
102.4
[μs]
High-going
Low-going
6.4
1.6
0.4
DV1CK = 0
Maximum Time Setting
26.11
[ms]
1.63
0.41
0.10
Page 115
NORMAL, IDLE Mode
NORMAL, IDLE mode
Minimum Pulse Width
2
2
Resolution
3
3
/fc
/fc
204.8
12.8
[μs]
3.2
0.8
DV1CK = 1
Maximum Time Setting
52.22
[ms]
3.28
0.82
0.20
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