tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 137

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tmp88fw45afg

Manufacturer Part Number
tmp88fw45afg
Description
8 Bit Microcontroller Tlcs-870/x Series
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
Example :Setting the timer mode with source clock fc/2
13.3
13.3.1
bit pulse width modulation (PWM) output modes. The TimerCounter 5 and 6 (TC5, 6) are cascadable to form a 16-
bit timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, 16-bit pulse width
modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes.
The TimerCounter 5 and 6 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8-
(TimerCounter6, fc = 20.0 MHz)
Function
and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is cleared.
After being cleared, the up-counter restarts counting.
Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output pulses.
Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the
Note 3: j = 5, 6
In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter
8-Bit Timer Mode (TC5 and 6)
shift register configuration in the timer mode, the new value programmed in TTREGj is in effect immediately
after the programming. Therefore, if TTREGi is changed while the timer is running, an expected operation
may not be obtained.
LD
DI
SET
EI
LD
LD
Table 13-3 Source Clock for TimerCounter 5, 6 (Internal Clock)
DV1CK = 0
fc/2
fc/2
fc/2
fc/2
(TTREG6), 0AH
(EIRC). EF37
(TC6CR), 00010000B
(TC6CR), 00011000B
11
NORMAL, IDLE mode
[Hz]
7
5
3
Source Clock
DV1CK = 1
fc/2
fc/2
fc/2
fc/2
12
[Hz]
8
6
4
7
Page 123
Hz and generating an interrupt 64 μs later
: Sets the timer register (80 μs ÷ 2
: Enables INTTC6 interrupt.
: Sets the operating cock to fc/2
: Starts TC6.
fc = 20 MHz
DV1CK = 0
Resolution
128 μs
500 ns
8 μs
2 μs
Repeated Cycle
fc = 20 MHz
DV1CK = 0
127.5 μs
32.6 ms
510 μs
2.0 ms
7
, and 8-bit timer mode.
7
/fc = 0AH).
TMP88FW45AFG

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