m58wr064kt Numonyx, m58wr064kt Datasheet - Page 9

• Manufacturer Part Number: m58wr064kt
• Description: 16-, 32-, 64-mbit ?16, Multiple Bank, Burst 1.8 V Supply Flash Memories
• Manufacturer: Numonyx

M58WRxxxKT, M58WRxxxKB
1
Description
The M58WR016KT/B, M58WR032KT/B and M58WR064KT/B are 16 Mbit (1 Mbit ×16),
32 Mbit (2 Mbit ×16) and 64 Mbit (4 Mbit ×16) non-volatile Flash memories, respectively.
They may be erased electrically at block level and programmed in-system on a word-by-
word basis using a 1.7 V to 2 V V
for the Input/Output pins. An optional 9 V V
customer programming.
The M58WRxxxKT/B feature an asymmetrical block architecture.
●
●
●
The multiple bank architecture allows dual operations. While programming or erasing in one
bank, read operations are possible in other banks. Only one bank at a time is allowed to be
in program or erase mode. It is possible to perform burst reads that cross bank boundaries.
The bank architectures are summarized in
maps are shown in
top of the memory address space for the M58WR016KT, M58WR032KT and
M58WR064KT, and at the bottom for the M58WR016KB, M58WR032KB and
M58WR064KB.
Each block can be erased separately. Erase can be suspended to perform program in any
other block, and then resumed. Program can be suspended to read data in any other block
and then resumed. Each block can be programmed and erased over 100 000 cycles using
the supply voltage V
speed up programming.
Program and erase commands are written to the command interface of the memory. An
internal Program/Erase Controller manages the timings necessary for program and erase
operations. The end of a program or erase operation can be detected and any error
conditions identified in the Status Register. The command set required to control the
memory is consistent with JEDEC standards.
The device supports synchronous burst read and asynchronous read from all blocks of the
memory array; at power-up the device is configured for asynchronous read. In synchronous
burst mode, data is output on each clock cycle at frequencies of up to 66 MHz. The
synchronous burst read operation can be suspended and resumed.
The device features an automatic standby mode. When the bus is inactive during
asynchronous read operations, the device automatically switches to the automatic standby
mode. In this condition the power consumption is reduced to the standby value I
outputs are still driven.
The M58WR016KT/B has an array of 39 blocks, and is divided into 4 Mbit banks. There
are 3 banks each containing 8 main blocks of 32 Kwords, and one parameter bank
containing 8 parameter blocks of 4 Kwords and 7 main blocks of 32 Kwords.
The M58WR032KT/B has an array of 71 blocks, and is divided into 4 Mbit banks. There
are 7 banks each containing 8 main blocks of 32 Kwords, and one parameter bank
containing 8 parameter blocks of 4 Kwords and 7 main blocks of 32 Kwords.
The M58WR064KT/B has an array of 135 blocks, and is divided into 4 Mbit banks.
There are 15 banks each containing 8 main blocks of 32 Kwords, and one parameter
bank containing 8 parameter blocks of 4 Kwords and 7 main blocks of 32 Kwords.
Figure
DD
. Two enhanced factory programming commands are available to
4,
Figure 5
DD
supply for the circuitry and a 1.7 V to 2 V V
and
Figure
Table
PP
power supply is provided to speed up
2,
6. The parameter blocks are located at the
Table 3
and
Table 4
and the memory
Description
DD4
DDQ
and the
supply
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