m58wr064kt Numonyx, m58wr064kt Datasheet - Page 52

• Manufacturer Part Number: m58wr064kt
• Description: 16-, 32-, 64-mbit ?16, Multiple Bank, Burst 1.8 V Supply Flash Memories
• Manufacturer: Numonyx

Read modes
9.2
52/125
Synchronous burst read mode
In synchronous burst read mode the data is output in bursts synchronized with the clock. It
is possible to perform burst reads across bank boundaries.
Synchronous burst read mode can only be used to read the memory array. For other read
operations, such as read Status Register, read CFI, and read electronic signature, single
synchronous read or asynchronous random access read must be used.
In synchronous burst read mode the flow of the data output depends on parameters that are
configured in the Configuration Register.
A burst sequence is started at the first clock edge (rising or falling depending on valid clock
edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip
Enable, whichever occurs last. Addresses are internally incremented and after a delay of 2
to 5 clock cycles (X latency bits CR13-CR11) the corresponding data is output on each
clock cycle.
The number of words to be output during a synchronous burst read operation can be
configured as 4, 8, 16 words, or continuous (burst length bits CR2-CR0). The data can be
configured to remain valid for one or two clock cycles (data output configuration bit CR9).
The order of the data output can be modified through the burst type and the wrap burst bits
in the Configuration Register. The burst sequence may be configured to be sequential or
interleaved (CR7). The burst reads can be confined inside the 4, 8 or 16 word boundary
(wrap) or overcome the boundary (no wrap). If the starting address is aligned to the burst
length (4, 8 or 16 words) the wrapped configuration has no impact on the output sequence.
Interleaved mode is not allowed in continuous burst read mode or with no wrap sequences.
A WAIT signal may be asserted to indicate to the system that an output delay occurs. This
delay depends on the starting address of the burst sequence. The worst case delay occurs
when the sequence is crossing a 16-word boundary and the starting address was at the end
of a four word boundary.
WAIT is asserted during X latency, the Wait state, and at the end of 4-, 8- or 16-word burst.
It is only de-asserted when output data are valid. In continuous burst read mode a Wait state
occurs when crossing the first 16-word boundary. If the burst starting address is aligned to a
4-word page, the Wait state does not occur.
The WAIT signal can be configured to be active Low or active High by setting CR10 in the
Configuration Register. The WAIT signal is meaningful only in synchronous burst read
mode. In other modes, WAIT is always asserted (except for read array mode).
See
AC waveforms
Table 25: Synchronous read AC characteristics
for details.
and
Figure 14: Synchronous burst read
M58WRxxxKT, M58WRxxxKB