m58wr064kt Numonyx, m58wr064kt Datasheet - Page 44

• Manufacturer Part Number: m58wr064kt
• Description: 16-, 32-, 64-mbit ?16, Multiple Bank, Burst 1.8 V Supply Flash Memories
• Manufacturer: Numonyx

Configuration Register
8
8.1
8.2
8.3
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Configuration Register
The Configuration Register configures the type of bus access that the memory performs.
Refer to
The Configuration Register is set through the command interface. After a reset or power-up
the device is configured for asynchronous page read (CR15 = 1). The Configuration
Register bits are described in
type, burst X latency, and the Read operation. Refer to Figures
synchronous burst configurations.
Read select bit (CR15)
The read select bit, CR15, switches between asynchronous and synchronous bus read
operations. When the read select bit is set to ’1’, read operations are asynchronous; when
the read select bit is set to ’0’, read operations are synchronous. Synchronous burst read is
supported in both parameter and main blocks and can be performed across banks.
On reset or power-up the read select bit is set to’1’ for asynchronous access.
X-latency bits (CR13-CR11)
The X-latency bits are used during synchronous read operations to set the number of clock
cycles between the address being latched and the first data becoming available. For correct
operation the X-latency bits can only assume the values in
Table
the device and the frequency used to read the Flash memory in synchronous mode.
Table 11.
Wait polarity bit (CR10)
In synchronous burst mode the Wait signal indicates whether the output data are valid or a
WAIT state must be inserted. The wait polarity bit is used to set the polarity of the Wait
signal. When the wait polarity bit is set to ‘0’ the Wait signal is active Low. When the wait
polarity bit is set to ‘1’ the Wait signal is active High.
11shows how to set the X-latency parameter, taking into account the speed class of
Section 9: Read modes
30 MHz
40 MHz
54 MHz
66 MHz
Latency settings
fmax
Table
for details on read operations.
12. They specify the selection of the burst length, burst
t
33 ns
25 ns
19 ns
15 ns
K
min
Table 12: Configuration
M58WRxxxKT, M58WRxxxKB
8
and
9
X-latency min
for examples of
2
3
4
4
Register.