fm93c46 Fairchild Semiconductor, fm93c46 Datasheet
fm93c46
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fm93c46 Summary of contents
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... CMOS process for high reliability, high endurance and low power consumption. “LZ” and “L” versions of FM93C46 offer very low standby current making them suitable for low power applications. This device is offered in both SO and TSSOP packages for small space consid- erations ...
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... Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care should be taken that the voltage applied on these pins does not exceed the FM93C46 Rev. D ...
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... CSH t DI Hold Time DIH t Output Delay Status Valid Hi Write Cycle Time WP FM93C46 Rev. D.1 (Note 1) -65°C to +150°C Ambient Operating Temperature FM93C46 +6.5V to -0.3V FM93C46E FM93C46V +300°C Power Supply ( 2000V V = 4.5V to 5.5V unless otherwise specified SK=1 ...
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... KHz (Note 5) C Output Capacitance OUT C Input Capacitance IN 2.7V ≤ V ≤ 5.5V 0.3V/1.8V CC (Extended Voltage Levels) 4.5V ≤ V ≤ 5.5V 0.4V/2.4V CC (TTL Levels) FM93C46 Rev. D.1 (Note 1) -65°C to +150°C Ambient Operating Temperature FM93C46L/LZ +6.5V to -0.3V FM93C46LE/LZE FM93C46LV/LZV +300°C Power Supply ( 2000V V = 2.7V to 4.5V unless otherwise specified. Refer ...
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... This is an active high input pin to FM93C46 EEPROM (the device) and is generated by a master that is controlling the device. A high level on this pin selects the device and a low level deselects the device. All serial communications with the device is enabled only when this pin is held high. However this pin cannot be permanently ...
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... DC and AC Electrical Characteristics table) for the internal programming cycle to finish. During this time, the device remains busy and is not ready for another instruction. FM93C46 Rev. D.1 The status of the internal programming cycle can be polled at any time by bringing the CS signal high again, after t CS signal is high, the DO pin indicates the READY/BUSY status of the chip ...
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... ALL” instructions are included to maintain compatibility with earlier technology EEPROMs.Clearing of Ready/Busy status When programming is in progress, the Data-Out pin will display FM93C46 Rev. D.1 the programming status as either BUSY (low) or READY (high) when CS is brought high (DO output will be tri-stated when CS is low) ...
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... WRITE ENABLE CYCLE (WEN > > FM93C46 Rev. D SKH SKL t DIH Valid Input t ...
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... > > > FM93C46 Rev. D ...
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... > CLEARING READY STATUS High - Z DO Note: This Star t bit can also be par next instr uction. Hence the cycle can be continued (instead of getting ter minated, as shown new instr uction is being issued. FM93C46 Rev. D ...
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... All lead tips Typ. All Leads FM93C46 Rev. D.1 0.189 - 0.197 (4.800 - 5.004 0.228 - 0.244 (5.791 - 6.198 Lead #1 IDENT 0.053 - 0.069 (1.346 - 1.753) 8¡ ...
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... Pin #1 IDENT 0.0433 Max (1.1) 0.0256 (0.65) Typ. Notes: Unless otherwise specified 1. Reference JEDEC registration MO153. Variation AA. Dated 7/93 FM93C46 Rev. D.1 5 0.169 - 0.177 (4.30 - 4.50) (1.78) Typ (0.42) Typ Land pattern recommendation 4 See detail A 0.002 - 0.006 (0.05 - 0.15) 0.0075 - 0.0118 (0.19 - 0.30) 0¡-8¡ DETAIL A Typ. Scale: 40X ...
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... English Français Italiano Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. FM93C46 Rev. D.1 0.373 - 0.400 (9.474 - 10.16) 0.090 (2.286) ...