psd813f1a-90ut STMicroelectronics, psd813f1a-90ut Datasheet - Page 7

• Manufacturer Part Number: psd813f1a-90ut
• Description: Flash In-system Programmable Isp Peripherals For 8-bit Mcus
• Manufacturer: STMicroelectronics

5.0
PSD913F1
Architectural
Overview
6
PSD913F1
PSD913F1 devices contain several major functional blocks. Figure 1 on page 3 shows the
architecture of the PSD913F1 device. The functions of each block are described briefly in
the following sections. Many of the blocks perform multiple functions and are user config-
urable.
5.1 Memory
The PSD913F1 contains the following memories:
Each of the memories is briefly discussed in the following paragraphs. A more detailed
discussion can be found in section 9.
The 1 Mbit Flash is the main memory of the PSD913F1. It is divided into eight equally-sized
sectors that are individually selectable.
The 256 Kbit EEPROM or Flash is divided into four equally-sized sectors. Each sector is
individually selectable.
The 16 Kbit SRAM is intended for use as a scratchpad memory or as an extension to the
microcontroller SRAM. If an external battery is connected to the PSD913F1’s Vstby pin,
data will be retained in the event of a power failure.
Each block of memory can be located in a different address space as defined by the user.
The access times for all memory types includes the address latching and DPLD decoding
time.
5.2 Page Register
The eight-bit Page Register expands the address range of the microcontroller by up to
256 times.The paged address can be used as part of the address space to access external
memory and peripherals or internal memory and I/O. The Page Register can also be used
to change the address mapping of blocks of Flash memory into different memory spaces for
in-circuit reprogramming.
5.3 PLDs
The device contains two combinatorial PLD blocks, each optimized for a different function,
as shown in Table 2. The functional partitioning of the PLDs reduces power consumption,
optimizes cost/performance, and eases design entry.
The Decode PLD (DPLD) is used to decode addresses and generate chip selects for the
PSD913F1 internal memory and registers. The general purpose PLD (GPLD) can
implement user-defined external chip selects and logic functions. The PLDs receive their
inputs from the PLD Input Bus and are differentiated by their output destinations, number of
Product Terms.
The PLDs consume minimal power by using Zero-Power design techniques. The speed
and power consumption of the PLD is controlled by the Turbo Bit (ZPSD only) in the
PMMR0 register and other bits in the PMMR2 registers. These registers are set by the
microcontroller at runtime. There is a slight penalty to PLD propagation time when invoking
the ZPSD features.
Table 2. PLD I/O Table
Decode PLD
General Purpose PLD
•
•
•
A 1 Mbit Flash
A secondary 256 Kbit EEPROM memory
A 16 Kbit SRAM.
Name
Abbreviation
DPLD
GPLD
Inputs
57
57
Outputs
15
19
Product Terms
114
Preliminary
39