cyv15g0404dxb Cypress Semiconductor Corporation., cyv15g0404dxb Datasheet - Page 35

• Manufacturer Part Number: cyv15g0404dxb
• Description: Independent Clock Quad Hotlink Ii Transceiver With Reclocker
• Manufacturer: Cypress Semiconductor Corporation.

Table 11. Package Coordinate Signal Allocation (continued)
Document #: 38-02097 Rev. *B
Ball
C04
C05
C06
M03
M04
M17
M18
M19
M20
N01
N02
N03
N04
N17
N18
N19
N20
R01
R02
R03
R04
R17
R18
R19
R20
U01
U02
P01
P02
P03
P04
P17
P18
P19
P20
T01
T02
T03
T04
T17
T18
T19
T20
ID
Signal Name
REFCLKB+
REFCLKB–
RCLKENC
TXCLKOC
RXCLKC+
RXCLKC–
RXSTC[0]
RXSTC[1]
RXSTC[2]
TXCTB[1]
TXERRC
TXERRB
TXCLKB
RXDC[1]
RXDC[0]
TXDD[0]
TXDD[1]
TXDB[5]
TXDB[4]
TXDB[3]
TXDB[2]
TXDB[1]
TXDB[0]
TXDB[7]
INSELB
ULCD
VCC
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
LVTTL IN PU
LVTTL IN PD
LVTTL IN PD
Signal Type
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
PECL IN
PECL IN
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
W01
W02
Ball
U03
U04
U05
U06
U07
U08
U09
U10
U12
U13
U14
U15
U16
U17
U18
U19
U20
V05
V06
V07
V08
V13
V14
V15
V16
V17
V19
V20
F02
F03
F04
U11
V01
V02
V03
V04
V09
V10
V11
V12
V18
ID
Signal Name
REFCLKD–
REFCLKD+
RCLKEND
TXCLKOA
RXSTD[0]
RXSTD[2]
TXCTD[1]
TXCTB[0]
RXSTA[2]
RXSTA[1]
TXCTD[0]
RXSTA[0]
TXCTA[1]
ADDR [0]
TXCTA[0]
ADDR [2]
RXDC[7]
RXDD[2]
RXDD[1]
RXDD[6]
RXDD[3]
TXDC[0]
TXDD[2]
TXDA[1]
TXDA[4]
RXDA[2]
TXDD[3]
TXDD[4]
TXDA[3]
TXDA[7]
RXDA[7]
RXDA[3]
RXDA[0]
TXDD[5]
TXDD[7]
GND
GND
GND
GND
VCC
VCC
VCC
VCC
LVTTL IN PD
LVTTL IN PU
LVTTL IN PU
Signal Type
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
GROUND
GROUND
GROUND
GROUND
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
PECL IN
PECL IN
POWER
POWER
POWER
POWER
W03
W04
W05
W06
W07
W08
W09
W10
W12
W13
W14
W15
W16
W17
W18
W19
W20
M01
M02
W11
Ball
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Y09
Y10
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
L20
Y11
ID
Signal Name
REFCLKA+
REFCLKA–
TXCLKOD
RXCLKD–
RXCLKA+
RXCLKD+
RXSTD[1]
RXCLKA–
ADDR [3]
ADDR [1]
TXERRA
TXERRD
RXDC[4]
RXDC[5]
RXDD[4]
RXDA[4]
RXDA[1]
TXCLKD
RXDD[7]
RXDD[5]
RXDD[0]
TXCLKA
RXDA[6]
RXDA[5]
TXDB[6]
TXDA[2]
TXDA[6]
TXDD[6]
TXDA[0]
TXDA[5]
LFID
GND
GND
GND
GND
VCC
VCC
LFIA
VCC
VCC
NC
CYV15G0404DXB
NO CONNECT
LVTTL IN PU
LVTTL IN PU
LVTTL IN PD
LVTTL IN PD
Signal Type
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
GROUND
GROUND
GROUND
GROUND
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
POWER
POWER
PECL IN
POWER
POWER
PECL IN
Page 35 of 44
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