cyv15g0404dxb Cypress Semiconductor Corporation., cyv15g0404dxb Datasheet - Page 14

• Manufacturer Part Number: cyv15g0404dxb
• Description: Independent Clock Quad Hotlink Ii Transceiver With Reclocker
• Manufacturer: Cypress Semiconductor Corporation.

Transmit Modes
Encoder Bypass
When the Encoder is bypassed, the character captured from the
TXDx[7:0] and TXCTx[1:0] input register is passed directly to the
transmit shifter without modification. With the encoder bypassed,
the TXCTx[1:0] inputs are considered part of the data character
and do not perform a control function that would otherwise
modify the interpretation of the TXDx[7:0] bits. The bit usage and
mapping of these control bits when the Encoder is bypassed is
shown in
Table 2. Encoder Bypass Mode
When the encoder is enabled, the TXCTx[1:0] data control bits
control the interpretation of the TXDx[7:0] bits and the characters
generated by them. These bits are interpreted as listed in
Table
Table 3. Transmit Modes
Word Sync Sequence
When TXCTx[1:0] = 11, a 16-character sequence of K28.5
characters, known as a word sync sequence, is generated on the
associated channel. This sequence of K28.5 characters may
start with either a positive or negative disparity K28.5 (as deter-
mined by the current running disparity and the 8B/10B coding
rules). The disparity of the second and third K28.5 characters in
this sequence are reversed from what normal 8B/10B coding
rules would generate. The remaining K28.5 characters in the
sequence follow all 8B/10B coding rules. The disparity of the
generated K28.5 characters in this sequence follow a pattern of
either ++––+–+–+–+–+–+– or ––++–+–+–+–+–+–+.
The generation of this sequence, once started, cannot be
stopped until all 16 characters have been sent. The content of
the associated input registers are ignored for the duration of this
Document #: 38-02097 Rev. *B
TXCTx[1]
TXCTx[1] (MSB)
TXDx[0] (LSB)
Signal Name
TXCTx[0]
0
0
1
1
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
3.
Table
TXCTx[0]
2.
0
1
0
1
Bus Weight
Encoded data character
K28.5 fill character
Special character code
16-character Word Sync Sequence
2
2
2
2
2
2
2
2
2
2
0
1
2
3
4
5
6
7
8
9
Characters Generated
10B Name
a
b
c
d
e
g
h
[7]
i
f
j
sequence. At the end of this sequence, if the TXCTx[1:0] = 11
condition is sampled again, the sequence restarts and remains
uninterruptible for the following 15 character clocks.
Transmit BIST
Each transmit channel contains an internal pattern generator that
can be used to validate both the link and device operation. These
generators are enabled by the associated TXBISTx latch
through the device configuration interface. When enabled, a
register in the associated transmit channel becomes a signature
pattern generator by logically converting to a Linear Feedback
Shift Register (LFSR). This LFSR generates a 511-character (or
526-character) sequence that includes all data and special
character codes, including the explicit violation symbols. This
provides a predictable yet pseudo-random sequence that can be
matched to an identical LFSR in the attached Receiver(s).
A device reset (RESET sampled LOW) presets the BIST enable
latches to disable BIST on all channels.
All data and data-control information present at the associated
TXDx[7:0] and TXCTx[1:0] inputs are ignored when BIST is
active on that channel. If the receive channels are configured for
reference clock operation, each pass is preceded by a
16-character word sync sequence to allow elasticity buffer
alignment and management of clock frequency variations.
Transmit PLL Clock Multiplier
Each Transmit PLL Clock Multiplier accepts a character rate or
half character-rate external clock at the associated REFCLKx±
input, and that clock is multiplied by 10 or 20 (as selected by
TXRATEx) to generate a bit rate clock for use by the transmit
shifter. It also provides a character rate clock used by the
transmit paths, and outputs this character rate clock as
TXCLKOx.
Each clock multiplier PLL is able to accept a REFCLKx± input
between 19.5 MHz and 150 MHz, however, this clock range is
limited by the operating mode of the CYV15G0404DXB clock
multiplier (TXRATEx) and by the level on the associated
SPDSELx input.
SPDSELx are 3-level select
operating ranges for the serial data outputs and inputs of the
associated channel. The operating serial signaling rate and
allowable range of REFCLKx± frequencies are listed in
Table 4. Operating Speed Settings
MID (Open)
SPDSELx
HIGH
LOW
TXRATE
1
0
1
0
1
0
[4]
REFCLKx±
Frequency
inputs that select one of three
19.5 – 40
reserved
80 – 150
20 – 40
40 – 80
40 – 75
CYV15G0404DXB
(MHz)
Rate (MBaud)
800 – 1500
Signaling
195 – 400
400 – 800
Page 14 of 44
Table
4.
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