cyv15g0404dxb Cypress Semiconductor Corporation., cyv15g0404dxb Datasheet - Page 28

• Manufacturer Part Number: cyv15g0404dxb
• Description: Independent Clock Quad Hotlink Ii Transceiver With Reclocker
• Manufacturer: Cypress Semiconductor Corporation.

CYV15G0404DXB AC Electrical Characteristics
Document #: 38-02097 Rev. *B
CYV15G0404DXB Transmitter LVTTL Switching Characteristics
f
t
t
t
t
t
t
t
f
t
t
CYV15G0404DXB Receiver LVTTL Switching Characteristics
f
t
t
t
t
t
t
CYV15G0404DXB REFCLKx Switching Characteristics
f
t
t
t
t
t
t
Notes
TS
TXCLK
TXCLKH
TXCLKL
TXCLKR
TXCLKF
TXDS
TXDH
TOS
TXCLKO
TXCLKOD
RS
RXCLKP
RXCLKD
RXCLKR
RXCLKF
RXDv–
RXDv+
REF
REFCLK
REFH
REFL
REFD
REFR
REFF
20. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
21. The ratio of rise time to falling time must not vary by greater than 2:1.
22. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
23. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.
24. Receiver UI (Unit Interval) is calculated as 1/(f
25. The duty cycle specification is a simultaneous condition with the t
Parameter
cannot be as large as 30%–70%.
[20, 21, 22]
[25]
[20, 21, 22]
[23]
[23]
[20]
[20]
[20, 21, 22]
[20, 21, 22]
[20]
[20]
TXCLKx Clock Cycle Frequency
TXCLKx Period=1/f
TXCLKx HIGH Time
TXCLKx LOW Time
TXCLKx Rise Time
TXCLKx Fall Time
Transmit Data Set-up Time to TXCLKx↑ (TXCKSELx ≠ 0)
Transmit Data Hold Time from TXCLKx↑ (TXCKSELx ≠ 0)
TXCLKOx Clock Frequency = 1x or 2x REFCLKx Frequency
TXCLKOx Period=1/f
TXCLKO Duty Cycle centered at 60% HIGH time
RXCLKx± Clock Output Frequency
RXCLKx± Period = 1/f
RXCLKx± Duty Cycle Centered at 50% (Full Rate and Half Rate when
RXCKSELx = 0)
RXCLKx± Rise Time
RXCLKx± Fall Time
Status and Data Valid Time to RXCLKx± (RXRATEx = 0, RXCKSELx = 0)
(Full Rate)
Status and Data Valid Time to RXCLKx± (RXRATEx = 1, RXCKSELx = 0)
(Half Rate)
Status and Data Valid Time to RXCLKx± (RXRATEx = 0, RXCKSELx = 0)
(Full Rate)
Status and Data Valid Time to RXCLKx± (RXRATEx = 1, RXCKSELx =0)
(Half Rate)
REFCLKx Clock Frequency
REFCLKx Period = 1/f
REFCLKx HIGH Time (TXRATEx = 1)(Half Rate)
REFCLKx HIGH Time (TXRATEx = 0)(Full Rate)
REFCLKx LOW Time (TXRATEx = 1)(Half Rate)
REFCLKx LOW Time (TXRATEx = 0)(Full Rate)
REFCLKx Duty Cycle
REFCLKx Rise Time (20%–80%)
REFCLKx Fall Time (20%–80%)
TS
REF
TOS
RS
REF
* 20) (when TXRATEx = 1) or 1/(f
Description
REFH
and t
REFL
REF
parameters. This means that at faster character rates the REFCLKx± duty cycle
Over the Operating Range
* 10) (when TXRATEx = 0). In an operating link this is equivalent to t
Over the Operating Range
Over the Operating Range
5UI–2.0
5UI–1.3
5UI–1.8
5UI–2.6
2.9
2.9
Min.
19.5
6.66
19.5
6.66
–1.9
9.75
6.66
–1.0
19.5
2.2
2.2
0.2
0.2
2.2
1.0
0.3
0.3
6.6
5.9
5.9
30
[20]
[20]
[24]
[24]
[24]
[24]
CYV15G0404DXB
102.56
51.28
51.28
51.28
Max
+1.0
150
150
150
150
1.7
1.7
1.2
1.2
70
0
2
2
Page 28 of 44
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MHz
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MHz
Unit
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ns
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