cyv15g0404dxb Cypress Semiconductor Corporation., cyv15g0404dxb Datasheet - Page 23

• Manufacturer Part Number: cyv15g0404dxb
• Description: Independent Clock Quad Hotlink Ii Transceiver With Reclocker
• Manufacturer: Cypress Semiconductor Corporation.

Device Configuration Strategy
The following is a series of ordered events needed to load the
configuration latches on a per channel basis:
Table 10. Device Control Latch Configuration Table
JTAG Support
The CYV15G0404DXB contains a JTAG port to allow system
level diagnosis of device interconnect. Of the available JTAG
modes, boundary scan, and bypass are supported. This
capability is present only on the LVTTL inputs and outputs and
the REFCLKx± clock input. The high-speed serial inputs and
outputs are not part of the JTAG test chain.
To ensure valid device operation after power up (including
non-JTAG operation), the JTAG state machine must also be
initialized to a reset state. This is done in addition to the device
Document #: 38-02097 Rev. *B
1. Pulse RESET Low after device power up. This operation
2. Set the static receiver latch bank for the target channel. May
3. Set the static transmitter latch bank for the target channel.
(0000b)
(0001b)
(0010b)
(0011b)
(0100b)
(0101b)
(0110b)
(0111b)
(1000b)
(1001b)
(1010b)
(1011b)
(1100b)
(1101b)
(1110b)
(1111b)
ADDR Channel Type
10
12
13
14
15
11
resets all four channels. Initialize the JTAG state machine to
its reset state as detailed in the
be performed using a global operation, if the application
permits it. [Optional step if the default settings match the
desired configuration.]
May be performed using a global operation, if the application
permits it. [Optional step if the default settings match the
desired configuration.]
0
1
2
3
4
5
6
7
8
9
GLOBAL
GLOBAL
GLOBAL
MASK
A
A
A
B
B
B
C
C
C
D
D
D
S
S
D
S
S
D
S
S
D
S
S
D
S
S
D
D
SDASEL2GL[1] SDASEL2GL[
RFMODEGL[1]
SDASEL2A[1]
SDASEL2B[1]
SDASEL2C[1]
SDASEL2D[1]
RFMODEA[1]
RFMODEB[1]
RFMODEC[1]
RFMODED[1]
RFENGL
RFENA
RFENB
RFENC
RFEND
DATA7
D7
JTAG Support
SDASEL2A[0]
SDASEL2B[0]
SDASEL2C[0]
SDASEL2D[0]
RFMODEA[0]
RFMODEB[0]
RFMODEC[0]
RFMODED[0]
RXPLLPDGL
RXPLLPDA
RXPLLPDB
RXPLLPDC
RXPLLPDD
RFMODE
DATA6
GL[0]
D6
0]
FRAMCHARGL DECMODEGL DECBYPGL RXCKSELGL RXRATEG
SDASEL1GL[1] SDASEL1GL[0
FRAMCHARA
SDASEL1A[1]
FRAMCHARB
SDASEL1B[1]
FRAMCHARC
SDASEL1C[1]
FRAMCHARD
SDASEL1D[1]
section.
RXBISTGL
RXBISTB
RXBISTC
RXBISTD
RXBISTA
DATA5
D5
SDASEL1A[0]
SDASEL1B[0]
SDASEL1C[0]
SDASEL1D[0]
DECMODEA
DECMODEB
DECMODEC
DECMODED
TXBISTGL
TXBISTC
TXBISTD
TXBISTA
TXBISTB
DATA4
D4
]
When a receive channel is configured with the decoder
bypassed and the receive clock selected as recovered clock in
half rate mode (DECBYPx = 0, RXRATEx = 0, RXCKSELx = 0),
the channel cannot be dynamically reconfigured to enable the
decoder with RXCLKx selected as the REFCLKx (DECBYPx =
1, RXCKSELx = 1). If such a change is desired, a global reset
should be performed and all channels should be reconfigured to
the desired settings.
reset (using RESET). The JTAG state machine is initialized using
TRST (asserting it LOW and de-asserting it or leaving it
asserted), or by asserting TMS HIGH for at least five consecutive
TCLK cycles. This is necessary to ensure that the JTAG
controller does not enter any of the test modes after device
power up. In this JTAG reset state, the rest of the device is in
normal operation.
Note. The order of device reset (using RESET) and JTAG initial-
ization does not matter.
4. Set the dynamic bank of latches for the target channel. Enable
5. Reset the Phase Alignment Buffer for the target channel. May
the Receive PLLs and transmit channels. May be performed
using a global operation, if the application permits it.
[Required step.]
be performed using a global operation, if the application
permits it. [Optional if phase align buffer is bypassed.]
DECBYPC
ENCBYPC
DECBYPD
ENCBYPD
DECBYPA
ENCBYPA
DECBYPB
ENCBYPB
ENCBPGL
DATA3
OE2GL
OE2A
OE2B
OE2C
OE2D
D3
TXCKSELGL TXRATEG
RXCKSELA
RXCKSELB
RXCKSELC
RXCKSELD
TXCKSELA
TXCKSELB
TXCKSELC
TXCKSELD
OE1GL
DATA2
OE1A
OE1B
OE1C
OE1D
D2
RXRATE D
RXRATEA
RXRATEB
RXRATEC
TXRATEC
PABRSTC
TXRATED
PABRSTD
PABRSTG
TXRATEA
PABRSTA
TXRATEB
PABRSTB
DATA1
D1
L
L
L
CYV15G0404DXB
GLEN10
FGLEN0
FGLEN1
FGLEN2
GLEN11
GLEN0
GLEN1
GLEN2
GLEN3
GLEN4
GLEN5
GLEN6
GLEN7
GLEN8
GLEN9
DATA0
D0
Page 23 of 44
10101101
10110011
10101101
10110011
10101101
10110011
10101101
10110011
10111111
10111111
10111111
10111111
11111111
Reset
Value
N/A
N/A
N/A
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