cyv15g0404dxb Cypress Semiconductor Corporation., cyv15g0404dxb Datasheet - Page 29

• Manufacturer Part Number: cyv15g0404dxb
• Description: Independent Clock Quad Hotlink Ii Transceiver With Reclocker
• Manufacturer: Cypress Semiconductor Corporation.

CYV15G0404DXB AC Electrical Characteristics
Document #: 38-02097 Rev. *B
t
t
t
t
t
t
t
CYV15G0404DXB Bus Configuration Write Timing Characteristics
t
t
t
CYV15G0404DXB JTAG Test Clock Characteristics
f
t
CYV15G0404DXB Device RESET Characteristics
t
CYV15G0404DXB Transmit Serial Outputs and TX PLL Characteristics Over the Operating Range
t
Notes
TREFDS
TREFDH
RREFDA
RREFDW
REFxDV–
REFxDV+
REFRX
DATAH
DATAS
WRENP
TCLK
TCLK
RST
B
26. Since this timing parameter is greater than the minimum time period of REFCLK it sets an upper limit to the frequency in which REFCLKx can be used to clock
27. Measured using a 50% duty cycle reference clock
28. REFCLKx± has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.
29. While sending continuous K28.5s, outputs loaded to a balanced 100Ω load, measured at the cross point of differential outputs, over the operating range.
30. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLKx± input, over the
31. Total jitter is calculated at an assumed BER of 1E -12. Hence: Total Jitter (tJ) = (tRJ * 14) + tDJ.
32. Also meets all Jitter Generation and Jitter Tolerance requirements as specified by SMPTE 259, SMPTE 292, ESCON, FICON, Fibre Channel, and DVB-ASI.
Parameter
Parameter
the receive data out of the output register. For predictable timing, users can use this parameter only if REFCLK period is greater than sum of t
time of the upstream device. When this condition is not true, RXCLKx± (a buffered or divided version of REFCLK when RXCKSELx = 1) could be used to clock
the receive data out of the device.
REFCLKx± must be within ±1500 PPM (±0.15%) of the transmitter PLL reference (REFCLKx±) frequency. Although transmitting to a HOTLink II receiver neces-
sitates the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be within the
limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard. For example, to be IEEE 802.3z Gigabit
Ethernet compliant, the frequency stability of the crystal needs to be within ±100 PPM.l.
operating range.
[28]
Transmit Data Set-up Time to REFCLKx - Full Rate
(TXRATEx = 0, TXCKSELx = 1)
Transmit Data Set-up Time to REFCLKx - Half Rate
(TXRATEx = 1, TXCKSELx = 1)
Transmit Data Hold Time from REFCLKx - Full Rate
(TXRATEx = 0, TXCKSELx = 1)
Transmit Data Hold Time from REFCLKx - Half Rate
(TXRATEx = 1, TXCKSELx = 1)
Receive Data Access Time to REFCLKx (RXCKSELx = 1)
Receive Data Valid Time Window (RXCKSELx = 1)
Received Data Valid Time to RXCLK when RXCKSELx = 1
(TXRATEx = 0, RXRATEx = 0)
Received Data Valid Time to RXCLK when RXCKSELx = 1
(TXRATEx = 0, RXRATEx = 1)
Received Data Valid Time to RXCLK when RXCKSELx = 1 (TXRATEx = 1) 10UI – 5.86
Received Data Valid Time from RXCLK when RXCKSELx = 1
(TXRATEx = 0, RXRATEx = 0)
Received Data Valid Time from RXCLK when RXCKSELx = 1
(TXRATEx = 0, RXRATEx = 1)
Received Data Valid Time from RXCLK when RXCKSELx = 1
(TXRATEx = 1)
REFCLKx Frequency Referenced to Received Clock Period
Bus Configuration Data Hold
Bus Configuration Data Setup
Bus Configuration WREN Pulse Width
JTAG Test Clock Frequency
JTAG Test Clock Period
Device RESET Pulse Width
Bit Time
Description
Description
Over the Operating Range
Over the Operating Range
(continued)
Condition
Over the Operating Range
10UI
5UI – 2.53
5UI – 1.83
10UI – 5.8
1.0
–0.15
5128
Min.
[24 ]
Min.
2.4
2.3
1.0
1.6
1.4
10
10
50
30
0
[27]
– 6.16
CYV15G0404DXB
[27]
[27]
[27]
9.7
+0.15
Max.
Max
666
20
RREFDA
[26]
Page 29 of 44
and set-up
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
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