cyv15g0404dxb Cypress Semiconductor Corporation., cyv15g0404dxb Datasheet - Page 13

• Manufacturer Part Number: cyv15g0404dxb
• Description: Independent Clock Quad Hotlink Ii Transceiver With Reclocker
• Manufacturer: Cypress Semiconductor Corporation.

Once initialized, TXCLKx is allowed to drift in phase as much as
±180 degrees. If the input phase of TXCLKx drifts beyond the
handling capacity of the phase align buffer, TXERRx is asserted
to indicate the loss of data, and remains asserted until the phase
align buffer is initialized. The phase of the TXCLKx relative to its
associated internal character rate clock is initialized when the
configuration latch PABRSTx is written as 0. When the
associated TXERRx is deasserted, the phase align buffer is
initialized and input characters are correctly captured.
Table 1. Input Register Bit Assignments
If the phase offset between the initialized location of the input
clock and REFCLKx exceeds the skew handling capabilities of
the phase align buffer, an error is reported on that channel’s
TXERRx output. This output indicates an error continuously until
the phase align buffer for that channel is reset. While the error
remains active, the transmitter for that channel outputs a
continuous C0.7 character to indicate to the remote receiver that
an error condition is present in the link.
Each phase align buffer may be individually reset with minimal
disruption of the serial data stream. When a phase align buffer
error is present, the transmission of a word sync sequence
recenters the phase align buffer and clears the error indication.
Note. K28.5 characters may be added or removed from the data
stream during the phase align buffer reset operation. When used
with non-Cypress devices that require a complete 16-character
word sync sequence for proper receive elasticity buffer
operation, follow the phase alignment buffer reset by a word sync
sequence to ensure proper operation.
Encoder
Each character received from the Input register or phase align
buffer is passed to the encoder logic. This block interprets each
character and any associated control bits, and outputs a 10-bit
transmission character.
Document #: 38-02097 Rev. *B
Note
7. LSB shifted out first.
TXCTx[1] (MSB)
TXDx[0] (LSB)
Signal Name
TXCTx[0]
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
Unencoded
DINx[0]
DINx[1]
DINx[2]
DINx[3]
DINx[4]
DINx[5]
DINx[6]
DINx[7]
DINx[8]
DINx[9]
[7]
Encoded
TXCTx[0]
TXCTx[1]
TXDx[0]
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
Depending on the operational mode, the generated transmission
character may be
■
■
■
■
■
■
Data Encoding
Raw data, as received directly from the transmit input register, is
seldom in a form suitable for transmission across a serial link.
The characters must usually be processed or transformed to
guarantee
■
■
■
■
When the encoder is enabled (ENCBYPx = 1), the characters
transmitted are converted from data or special character codes
to 10-bit transmission characters, using an integrated 8B/10B
encoder. When directed to encode the character as a special
character code, the encoder uses the special character encoding
rules listed in
as a data character, it is encoded using the data character
encoding rules in
The 8B/10B encoder is standards compliant with ANSI/NCITS
ASC X3.230-1994 Fibre Channel, IEEE 802.3z Gigabit Ethernet,
the IBM
ATM Forum standards for data transport.
Many of the special character codes listed in
generated
CYV15G0404DXB is designed to support two independent (but
non-overlapping) special character code tables. This allows the
CYV15G0404DXB to operate in mixed environments with other
Cypress HOTLink devices using the enhanced Cypress
command code set, and the reduced command sets of other
non-Cypress devices. Even when used in an environment that
normally uses non-Cypress Special Character codes, the
selective use of Cypress command codes can permit operation
where running disparity and error handling must be managed.
Following conversion of each input character from eight bits to a
10-bit transmission character, it is passed to the transmit shifter
and is shifted out LSB first, as required by ANSI and IEEE
standards for 8B/10B coded serial data streams.
The 10-bit preencoded character accepted in the input register.
The 10-bit equivalent of the 8-bit Data character accepted in
the input register
The 10-bit equivalent of the 8-bit Special Character code
accepted in the input register
The 10-bit equivalent of the C0.7 violation character if a phase
align buffer overflow or underflow error is present
A character that is part of the 511-character BIST sequence
A K28.5 character generated as an individual character or as
part of the 16-character Word Sync Sequence
a minimum transition density (to allow the receive PLL to extract
a clock from the serial data stream)
A DC-balance in the signaling (to prevent baseline wander)
Run length limits in the serial data (to limit the bandwidth
requirements of the serial link)
the remote receiver a way of determining the correct character
boundaries (framing)
®
ESCON
by
Table
Table
®
more
and FICON™ channels, ETSI DVB-ASI, and
15. When directed to encode the character
14.
than
one
CYV15G0404DXB
input
Table 15
character.
Page 13 of 44
may be
The
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