lan83c175 Standard Microsystems Corp., lan83c175 Datasheet - Page 45

• Manufacturer Part Number: lan83c175
• Description: Ethernet Cardbus Integrated Controller With Modem Support Corporation
• Manufacturer: Standard Microsystems Corp.

7 - ALTERNATE DIRECTION: When set, the
alternate data value is input from the MII
management data pin if serial management
interface is disabled.
6 - ALTERNATE DATA: Reading this bit
returns the value at the MII management data
pin. A value written to this bit will be driven
onto the MII management data pin when the
serial management interface is disabled and
the alternate direction bit is set to ouput.
5 - ALTERNATE CLOCK SOURCE:
register bit is muxed to the MII management
clock pin when
interface
management interface clock is set.
4
INTERFACE: This
serial management interface and a general
pupose interface muxed with the management
interface clock and data pins. When set, the
serial management interface is selected.
Default is set.
3 - PHY PRESENT: This bit is read only. It is
one value indicating the precence of a PHY
device.
2 - 694 LINK STATUS: This bit is read only
and returns the value of the 694LNK pin on
the LAN83C175.
1 - ENABLE 694: When set, the EN694 pin of
the LAN83C175 is driven to a logic one. When
clear, the EN694 pin is driven low.
0 - SERIAL MODE ENABLE: When set, the
MII interface functions serially
interface.
set to one when the MDIO line is at a logic
-
ENABLE
is
disabled.
SERIAL
bit selects between the
the serial management
When
MANAGEMENT
as a 7-wire
set,
This
the
45
This
LAN83C175 is connected to a 10 Mbps
PHY device.
operates
Reconciliation Sublayer and Media Independent
Interface Draft Standard.
3C - INTER-PACKET GAP
Reset Value: 011110001100000
This register is used to program the inter-packet
gap protocol timer. It contains two values. The
first 8 bit value is used to set the total inter-packet
gap time used by the transmit state machine for
deferral.
inter-frame spacing value used in the deference
process.
31 through 15 - Unused.
14 through 8 - INTERFRAME SPACING PART
ONE: This 7 bit value sets the first part of the
inter-frame spacing delay time. Default is 60 bit
times.
7 through 0 - INTERPACKET GAP TIME: This 8
bit value sets the inter-packet gap delay time.
Default is 96 bit times.
40 through 48 - LAN ADDRESS REGISTERS
Power Up Reset Value: Unknown
These registers hold the 48 bit LAN address for
the adapter.
after reset.
31 through 16: Unused.
15 through 0 - LAN ADDRESS: The Destination
address described as:
[N1][N0][N3][N2][N5][N4][N7][N6][N9][N8][N11][N10]
mode
The second 7 bit value sets the first
as
should
They are recalled from EEPROM
defined
When clear, the MII interface
be
by
enabled
the
IEEE
when
802.3u
serial
the